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S75WS256Nxx Based MCPs
Stacked Multi-Chip Product (MCP) 256 Megabit (16M x 16-bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst-mode Flash Memory with 128 Mb (8M x 16-Bit) CellularRAM and 512 Mb (32M x 16-bit) Data Storage
Data Sheet
PRELIMINARY
Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S75WS-N-00
Revision A
Amendment 0
Issue Date February 17, 2005
Advance
Information
This page intentionally left blank.
S75WS256Nxx Based MCPs
S75WS-N-00_A0 February 17, 2005
S75WS256Nxx Based MCPs
Stacked Multi-Chip Product (MCP) 256 Megabit (16M x 16-bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst-mode Flash Memory with 128 Mb (8M x 16-Bit) CellularRAM and 512 Mb (32M x 16-bit) Data Storage
Data Sheet
PRELIMINARY
General Description
The S75WS-N Series is a product line of stacked Multi-Chip Product (MCP) packages and consists of the following items: One or more S29WSxxxN code Flash CellularRAM One or more S29RS-N data storage Flash The products covered by this document are listed in the table below:
Device S75WS256NDF Code Flash Density 256 Mb RAM Density 128 Mb Data Storage Flash Density 512 Mb
Distinctive Characteristics
MCP Features
Power supply voltage of 1.7 V to 1.95 V High Performance -- 54 MHz, 66 MHz Packages -- 9 x 12 mm 84 ball FBGA Operating Temperature -- Wireless, -25C to +85C
Publication Number S75WS-N-00
Revision A
Amendment 0
Issue Date February 17, 2005
Advance
Information
Notice On Data Sheet Designations
Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions. Advance Information The Advance Information designation indicates that Spansion LLC is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion LLC therefore places the following conditions upon Advance Information content:
"This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice."
Preliminary The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content:
"This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications."
Combination Some data sheets will contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document will distinguish these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page. Full Production (No Designation on Document) When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion LLC applies the following conditions to documents in this category:
"This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion LLC deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur."
Questions regarding these document designations may be directed to your local AMD or Fujitsu sales office.
2
S75WS256Nxx Based MCPs
S75WS-N-00_A0 February 17, 2005
Advance
Information
Contents
S75WS256Nxx Based MCPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 2 3 4 5 Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Input/Output Descriptions and Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Connection Diagrams/Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1 Special Handling Instructions for FBGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2 Connection Diagram - Cellular Ram-Based Pinout, 9 x 12 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 5.3.1 Physical Dimensions - xxx084 - Fine Pitch Ball Grid Array 9 x 12 mm . . . . . . . . . . . . . . . . . . . . . . . . .16 5.4 Look-Ahead Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
S29PL256N MirrorBitTM Flash Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6 7 8
9
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Product Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.1 Device Operation Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.2 Asynchronous Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.3 Synchronous (Burst) Read Mode and Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.3.1 Continuous Burst Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.3.2 8-, 16-, 32-Word Linear Burst Read with Wrap Around . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.3.3 8-, 16-, 32-Word Linear Burst without Wrap Around . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.3.4 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.4 Autoselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.5 Program/Erase Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.5.1 Single Word Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.5.2 Write Buffer Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.5.3 Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.5.4 Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.5.5 Erase Suspend/Erase Resume Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.5.6 Program Suspend/Program Resume Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 8.5.7 Accelerated Program/Chip Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.5.8 Unlock Bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.5.9 Write Operation Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.6 Simultaneous Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.7 Writing Commands/Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.8 Handshaking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.9 Hardware Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.10 Software Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Advanced Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.1 Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.2 Persistent Protection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.3 Dynamic Protection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.4 Persistent Protection Bit Lock Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.5 Password Protection Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.6 Advanced Sector Protection Software Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.7 Hardware Data Protection Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.7.1 WP# Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.7.2 ACC Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.7.3 Low VCC Write Inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.7.4 Write Pulse Glitch Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.7.5 Power-Up Write Inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 S75WS256Nxx Based MCPs 3
February 17, 2005 S75WS-N-00_A0
Advance
Information
S29PL256N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
15 16 17 18
10 Power Conservation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 10.1 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 10.2 Automatic Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 10.3 Hardware RESET# Input Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 10.4 Output Disable (OE#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 11 Secured Silicon Sector Flash Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 11.1 Factory Secured SiliconSector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 11.2 Customer Secured Silicon Sector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 11.3 Secured Silicon Sector Entry and Secured Silicon Sector Exit Command Sequences. . . . . . . . . . . . . . . . . . . . . 63 12 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 12.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 12.2 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 12.3 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12.4 Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12.5 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12.6 VCC Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 12.7 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 12.8 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 12.8.1 CLK Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 12.8.2 Synchronous/Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 12.8.3 Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 12.8.4 AC Characteristics--Asynchronous Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 12.8.5 Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 12.8.6 Erase/Program Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 12.8.7 Erase and Programming Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 12.8.8 BGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 13 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 13.1 Common Flash Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 14 Commonly Used Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Device Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 18.1 Requirements for Asynchronous Read Operation (Non-Burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 18.2 Requirements for Synchronous (Burst) Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 18.2.1 Continuous Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 18.2.2 8-, 16-, and 32-Word Linear Burst with Wrap Around . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 18.2.3 8-, 16-, and 32-Word Linear Burst without Wrap Around . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 18.3 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 18.4 RDY: Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 18.5 Handshaking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 18.6 Writing Commands/Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 18.7 Accelerated Program/Chip Erase Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 18.8 Write Buffer Programming Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 18.9 Autoselect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 18.10 Dynamic Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 18.10.1 Dynamic Protection Bit (DYB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 18.11 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 18.12 Automatic Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 18.13 RESET#: Hardware Reset Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 18.14 Output Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 18.15 Hardware Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 18.15.1 Low VCC Write Inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 18.15.2 Write Pulse Glitch Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005
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18.15.3 Logical Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 18.15.4 Power-Up Write Inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 Sector Address / Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 19.1 Reading Array Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 19.2 Set Configuration Register Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 19.3 Read Configuration Register Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 19.3.1 Read Mode Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 19.3.2 Programmable Wait State Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 19.3.3 Programmable Wait State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 19.3.4 Boundary Crossing Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 19.3.5 Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 19.3.6 Burst Length Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 19.3.7 Burst Wrap Around . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 19.3.8 RDY Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 19.3.9 RDY Polarity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 19.4 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 19.5 Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 19.6 Autoselect Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 19.7 Program Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 19.8 Write Buffer Programming Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 19.8.1 Unlock Bypass Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 19.9 Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 19.10 Sector Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 19.10.1 Accelerated Sector Erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Erase Suspend/Erase Resume Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 20.1 Program Suspend/Program Resume Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 20.2 Volatile Sector Protection Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 22.1 DQ7: Data# Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 22.2 DQ6: Toggle Bit I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 22.3 Reading Toggle Bits DQ6/DQ2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 22.4 DQ5: Exceeded Timing Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 22.5 DQ3: Sector Erase Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 22.6 DQ1: Write to Buffer Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 25.1 CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 29.1 VCC Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 29.2 CLK Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 29.3 Synchronous/Burst Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 29.4 Asynchronous Mode Read @ VIO = 1.8 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 29.5 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 29.6 Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 29.7 Erase/Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 Erase and Programming Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
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31 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 32 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 32.1 Power-Up Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 33 Bus Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 33.1 Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 33.2 Page Mode Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 33.3 Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 33.4 Mixed-Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 33.5 Wait Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 33.6 LB#/UB# Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 34 Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 34.1 Standby Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 34.2 Temperature Compensated Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 34.3 Partial Array Refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 34.4 Deep Power-Down Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 35 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 35.1 Access Using CRE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 35.2 Bus Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 35.2.1 Burst Length (BCR[2:0]): Default = Continuous Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 35.2.2 Burst Wrap (BCR[3]): Default = No Wrap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 35.2.3 Output Impedance (BCR[5:4]): Default = Outputs Use Full Drive Strength . . . . . . . . . . . . . . . . . . . . . 166 35.2.4 Wait Configuration (BCR[8]): Default = Wait Transitions One Clock Before Data Valid/Invalid . . . . 167 35.2.5 Wait Polarity (BCR[10]): Default = Wait Active High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 35.2.6 Latency Counter (BCR[13:11]): Default = Three-Clock Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 35.2.7 Operating Mode (BCR[15]): Default = Asynchronous Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169 35.3 Refresh Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169 35.3.1 Partial Array Refresh (RCR[2:0]): Default = Full Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169 35.3.2 Deep Power-Down (RCR[4]): Default = DPD Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 35.3.3 Temperature Compensated Refresh (RCR[6:5]): Default = +85C Operation . . . . . . . . . . . . . . . . . . .170 35.3.4 Page Mode Operation (RCR[7]): Default = Disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 36 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 37 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 38 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 38.1 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 39 How Extended Timings Impact CellularRAMTM Operation. . . . . . . . . . . . . . . . . . . . . . . . . . 217 39.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 39.2 Asynchronous Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 39.2.1 Extended Write Timing-- Asynchronous Write Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218 39.3 Page Mode Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218 39.4 Burst-Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218 39.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218 40 Revisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
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Information
Tables
Table 2.1 Table 3.1 Table 7.1 Table 7.2 Table 7.3 Table 8.1 Table 8.2 Table 8.3 Table 8.4 Table 8.5 Table 8.6 Table 8.7 Table 8.8 Table 8.9 Table 8.10 Table 8.11 Table 8.12 Table 8.13 Table 8.14 Table 8.15 Table 8.16 Table 8.17 Table 8.18 Table 8.19 Table 8.20 Table 8.21 Table 8.22 Table 8.23 Table 8.24 Table 9.1 Table 9.2 Table 11.1 Table 11.2 Table 11.3 Table 11.4 Table 12.1 Table 13.1 Table 13.2 Table 13.3 Table 13.4 Table 13.5 Table 13.6 Table 18.1 Table 18.2 Table 18.3 Table 18.4 Table 18.5 Table 19.6 Table 19.7 Table 19.8 Table 19.9 MCP Configurations and Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 S29WS256N Sector & Memory Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 S29WS128N Sector & Memory Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 S29WS064N Sector & Memory Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Address Latency (S29WS256N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Address Latency (S29WS128N/S29WS064N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Address/Boundary Crossing Latency (S29WS256N @ 80/66 MHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Address/Boundary Crossing Latency (S29WS256N @ 54MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Address/Boundary Crossing Latency (S29WS128N/S29WS064N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Burst Address Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Autoselect Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Autoselect Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Autoselect Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Single Word Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Write Buffer Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Sector Erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Chip Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Erase Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Program Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Program Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Unlock Bypass Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Unlock Bypass Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Unlock Bypass Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Secured Silicon Sector Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Secured Silicon Sector Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Secured Silicon Sector Exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Memory Array Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Sector Protection Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 System Interface String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Address Latency Scheme for < 56Mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Address Latency Scheme for < 70Mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Address Latency Scheme for < 84Mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Burst Address Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Sector Address / Memory Address Map for the RS512N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Programmable Wait State Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Burst Length Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 19.10 Autoselect Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 19.11 Write Buffer Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
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Table 22.1 Table 24.1 Table 27.1 Table 27.2 Table 27.3 Table 31.1 Table 31.2 Table 31.3 Table 31.4 Table 31.5 Table 31.6 Table 31.7 Table 31.8 Table 33.1 Table 33.2 Table 33.3 Table 33.4 Table 34.1 Table 34.2 Table 34.3 Table 34.4 Table 34.5 Table 34.1 Table 34.2 Table 34.3 Table 34.4 Table 34.5 Table 34.6 Table 34.7 Table 34.8
Maximum Negative Overshoot Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Bus Operations--Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Bus Operations--Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Bus Configuration Register Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Sequence and Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Output Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Variable Latency Configuration Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Refresh Configuration Register Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 128Mb Address Patterns for PAR (RCR[4] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 64Mb Address Patterns for PAR (RCR[4] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 32Mb Address Patterns for PAR (RCR[4] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Temperature Compensated Refresh Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Partial Array Refresh Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Deep Power-Down Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Output Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Asynchronous Read Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Burst Read Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Asynchronous Write Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Burst Write Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Initialization Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Asynchronous Read Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Asynchronous Read Timing Parameters Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Asynchronous Read Timing Parameters--Page Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Burst Read Timing Parameters--Single Access, Variable Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Burst Read Timing Parameters--4-word Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Burst Read Timing Parameters--4-word Burst with LB#/UB# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Burst Read Timing Parameters--Burst Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 34.10 Burst Read Timing Parameters--BCR[8] = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Table 34.11 Asynchronous Write Timing Parameters--CE#-Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Table 34.12 Asynchronous Write Timing Parameters--LB#/UB#-Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Table 34.13 Asynchronous Write Timing Parameters--WE#-Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Table 34.14 Asynchronous Write Timing Parameters Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Table 34.15 Burst Write Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Table 34.16 Burst Write Timing Parameters--BCR[8] = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Table 34.17 Write Timing Parameters--Burst Write Followed by Burst Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Table 34.18 Read Timing Parameters--Burst Write Followed by Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Table 34.19 Write Timing Parameters--Asynchronous Write Followed by Burst Read. . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Table 34.20 Read Timing Parameters--Asynchronous Write Followed by Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Table 34.21 Asynchronous Write Timing Parameters--ADV# Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Table 34.22 Burst Read Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Table 34.24 Burst Read Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Table 34.25 Asynchronous Write Timing Parameters--WE# Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Table 34.27 Burst Read Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Table 34.28 Asynchronous Write Timing Parameters Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Table 34.30 Write Timing Parameters--ADV# Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Table 34.31 Read Timing Parameters--ADV# Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Table 34.33 Write Timing Parameters--Asynchronous Write Followed by Asynchronous Read . . . . . . . . . . . . . . . . . . . . 211 Table 34.34 Read Timing Parameters--Asynchronous Write Followed by Asynchronous Read . . . . . . . . . . . . . . . . . . . . . 211 Table 35.1 Extended Cycle Impact on Read and Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
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Figures
Figure 5.1 Figure 5.2 Figure 8.1 Figure 8.2 Figure 8.3 Figure 8.4 Figure 8.5 Figure 8.6 Figure 9.1 Figure 9.2 Figure 9.3 Figure 12.1 Figure 12.2 Figure 12.3 Figure 12.4 Figure 12.5 Figure 12.6 Figure 12.7 Figure 12.8 Figure 12.9 Connection Diagram - Cellular Ram-Based 84-ball Fine-Pitch Ball Grid Array .............................................15 Look Ahead Pinout - 1.8 V only x 16NOR + x16pSRAM + x16MirrorBit Data..............................................16 Synchronous/Asynchronous State Diagram...........................................................................................24 Synchronous Read ............................................................................................................................27 Single Word Program.........................................................................................................................33 Write Buffer Programming Operation ...................................................................................................37 Sector Erase Operation ......................................................................................................................39 Write Operation Status Flowchart ........................................................................................................46 Advanced Sector Protection/Unprotection .............................................................................................52 PPB Program/Erase Algorithm .............................................................................................................55 Lock Register Program Algorithm.........................................................................................................58 Maximum Negative Overshoot Waveform .............................................................................................65 Maximum Positive Overshoot Waveform ...............................................................................................65 Test Setup .......................................................................................................................................66 Input Waveforms and Measurement Levels ...........................................................................................66 VCC Power-up Diagram ......................................................................................................................67 CLK Characterization .........................................................................................................................69 CLK Synchronous Burst Mode Read......................................................................................................70 8-word Linear Burst with Wrap Around.................................................................................................71 8-word Linear Burst without Wrap Around ............................................................................................71
Figure 12.10 Linear Burst with RDY Set One Cycle Before Data ..................................................................................72 Figure 12.11 Asynchronous Mode Read...................................................................................................................73 Figure 12.12 Reset Timings...................................................................................................................................73 Figure 12.13 Chip/Sector Erase Operation Timings ...................................................................................................75 Figure 12.14 Asynchronous Program Operation Timings ............................................................................................76 Figure 12.15 Synchronous Program Operation Timings .............................................................................................77 Figure 12.16 Accelerated Unlock Bypass Programming Timing ...................................................................................77 Figure 12.17 Data# Polling Timings (During Embedded Algorithm) .............................................................................78 Figure 12.18 Toggle Bit Timings (During Embedded Algorithm) ..................................................................................78 Figure 12.19 Synchronous Data Polling Timings/Toggle Bit Timings ............................................................................79 Figure 12.20 DQ2 vs. DQ6 ....................................................................................................................................79 Figure 12.21 Latency with Boundary Crossing when Frequency > 66 MHz....................................................................80 Figure 12.22 Latency with Boundary Crossing into Program/Erase Bank ......................................................................81 Figure 12.23 Example of Wait State Insertion ..........................................................................................................82 Figure 12.24 Back-to-Back Read/Write Cycle Timings ...............................................................................................83 Figure 19.1 Figure 19.2 Figure 19.3 Figure 20.4 Figure 22.5 Figure 22.6 Figure 22.7 Figure 24.1 Figure 24.2 Figure 25.1 Figure 25.2 Figure 25.3 Figure 25.4 Figure 25.5 Figure 25.6 Figure 25.7 Figure 25.8 Figure 25.9 Synchronous/Asynchronous State Diagram......................................................................................... 110 Program Word Operation.................................................................................................................. 115 Write Buffer Programming Operation ................................................................................................. 116 Erase Operation .............................................................................................................................. 119 Data# Polling Algorithm ................................................................................................................... 122 Toggle Bit Algorithm ........................................................................................................................ 123 Maximum Positive Overshoot Waveform ............................................................................................. 125 Test Setup ..................................................................................................................................... 127 Input Waveforms and Measurement Levels ......................................................................................... 127 VCC Power-up Diagram .................................................................................................................... 128 CLK Characterization ....................................................................................................................... 128 CLK Synchronous Burst Mode Read.................................................................................................... 130 8-word Linear Burst with Wrap Around............................................................................................... 131 8-word Linear Burst without Wrap Around .......................................................................................... 131 Burst with RDY Set One Cycle Before Data.......................................................................................... 132 Asynchronous Mode Read with Latched Addresses ............................................................................... 133 Asynchronous Mode Read................................................................................................................. 133 Reset Timings................................................................................................................................. 134
Figure 25.10 Asynchronous Program Operation Timings: WE# Latched Addresses ...................................................... 136
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Figure 25.11 Synchronous Program Operation Timings: CLK Latched Addresses ......................................................... 137 Figure 25.12 Accelerated Unlock Bypass Programming Timing ................................................................................. 137 Figure 25.13 Data# Polling Timings (During Embedded Algorithm) ........................................................................... 138 Figure 25.14 Toggle Bit Timings (During Embedded Algorithm) ................................................................................ 138 Figure 25.15 Synchronous Data Polling Timings/Toggle Bit Timings .......................................................................... 139 Figure 25.16 DQ2 vs. DQ6 .................................................................................................................................. 139 Figure 25.17 Latency with Boundary Crossing........................................................................................................ 140 Figure 25.18 Example of Wait States Insertion ...................................................................................................... 140 Figure 25.19 Back-to-Back Read/Write Cycle Timings ............................................................................................. 141 Figure 27.1 Figure 28.2 Figure 29.1 Figure 29.2 Figure 29.3 Figure 29.4 Figure 29.5 Figure 29.6 Figure 29.7 Figure 29.8 Figure 31.1 Figure 31.2 Figure 31.3 Figure 31.4 Figure 31.5 Figure 31.6 Figure 34.1 Figure 34.2 Figure 34.3 Figure 34.4 Figure 34.5 Figure 34.6 Figure 34.7 Figure 34.8 Figure 34.9 Figure 34.9. Functional Block Diagram ................................................................................................................. 144 Power-Up Initialization Timing........................................................................................................... 148 Read Operation (ADV# Low)............................................................................................................. 149 Write Operation (ADV# Low) ............................................................................................................ 150 Page Mode Read Operation (ADV# Low)............................................................................................. 151 Burst Mode Read (4-word burst) ....................................................................................................... 152 Burst Mode Write (4-word burst)....................................................................................................... 152 Wired or Wait Configuration.............................................................................................................. 153 Refresh Collision During Read Operation............................................................................................. 154 Refresh Collision During Write Operation ............................................................................................ 155 Configuration Register Write, Asynchronous Mode Followed by Read ...................................................... 158 Configuration Register Write, Synchronous Mode Followed by Read0 ...................................................... 159 Wait Configuration (BCR[8] = 0) ....................................................................................................... 162 Wait Configuration (BCR[8] = 1) ....................................................................................................... 162 Wait Configuration During Burst Operation ......................................................................................... 163 Latency Counter (Variable Initial Latency, No Refresh Collision)............................................................. 163 AC Input/Output Reference Waveform ............................................................................................... 170 Output Load Circuit ......................................................................................................................... 170 Initialization Period.......................................................................................................................... 174 Asynchronous Read ......................................................................................................................... 175 Asynchronous Read Using ADV# ....................................................................................................... 177 Page Mode Read ............................................................................................................................. 179 Single-Access Burst Read Operation--Variable Latency ......................................................................... 181 Four-word Burst Read Operation--Variable Latency.............................................................................. 183 Four-word Burst Read Operation (with LB#/UB#) ................................................................................ 185 Continuous Burst Read Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition..................... 188
Figure 34.10 Refresh Collision During Write Operation ............................................................................................ 187 Figure 34.11 CE#-Controlled Asynchronous Write .................................................................................................. 189 Figure 34.12 LB#/UB#-Controlled Asynchronous Write ........................................................................................... 191 Figure 34.13 WE#-Controlled Asynchronous Write.................................................................................................. 193 Figure 34.14 Asynchronous Write Using ADV# ....................................................................................................... 195 Figure 34.15 Burst Write Operation ...................................................................................................................... 197 Figure 34.16 Continuous Burst Write Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition .................... 198 Figure 34.17 Burst Write Followed by Burst Read ................................................................................................... 199 Figure 34.18 Asynchronous Write Followed by Burst Read ....................................................................................... 200 Figure 34.19 Asynchronous Write (ADV# Low) Followed By Burst Read ..................................................................... 202 Figure 34.23. Burst Read Followed by Asynchronous Write (WE#-Controlled).............................................................. 204 Figure 34.26. Burst Read Followed by Asynchronous Write Using ADV# ..................................................................... 206 Figure 34.29. Asynchronous Write Followed by Asynchronous Read--ADV# Low .......................................................... 208 Figure 34.32. Asynchronous Write Followed by Asynchronous Read ........................................................................... 210 Figure 35.1 Figure 35.2 Figure 35.3 Extended Timing for tCEM ............................................................................................................................................... 212 Extended Timing for tTM................................................................................................................................................. 212 Extended Write Operation ................................................................................................................ 213
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S75WS-N-00_A0 February 17, 2005
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1
b
Product Selector Guide
Device Model Numbers MA MCP Configuration Code Flash Code DYB RAM Data Storage Flash pSRAM pSRAM Flash Power-Up Density Flash Density Speed Speed (Cellular RAM) Code pSRAM Data Storage Density State (Mb) (Mb/Gb) (MHz) (MHz) Supplier (Mb) Flash (Mb) (See Note) 54 WS256N 128 RS512N 256 128 512 Mb 66 66 54 0 1 0 1 2 9x12 Package 84 ball FBGA (mm)
S75WS256NDF
PA MB PB
Note: 0 (Protected), 1 (Unprotected [Default State])
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Ordering Information
The ordering part number is formed by a valid combination of the following: S75WS 256 N D F BA W M A
RAM Supplier; Speed Combination A = Cellular RAM2, 54 MHz B = Cellular RAM2, 66 MHz Package Dimensions and Ball Count; DYB Power Up; Flash Device Family (Data Storage) M = 1.4 mm, 9 x 12, 84 ball; 0; RS P = 1.4 mm, 9 x 12, 84 ball; 1; RS Temperature Range W = Wireless (-25C to +85C) Package Type And Material BA = Very Thin Fine-Pitch Ball Grid Array (BGA), Lead (Pb)-free Compliant Package BF = Very Thin Fine-Pitch Ball Grid Array (BGA), Lead (Pb)-free Package Data Storage Density F = 512 Mb Code Flash Density D = 128 Mb Process Technology N = 110 nm, Mirror Bit Technology Flash Density 256 = 256 Mb Device Family S75WS = Multi-chip Product (MCP) 1.8-volt Burst Mode Flash Memory, RAM, and NAND Data Storage
Table 2.1
S75WS256N D F
MCP Configurations and Valid Combinations
BA, BF Valid Combinations W M, P A, B
Package Marking Note: The BGA package marking omits the leading S75 and packing type designator from the ordering part number.
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations.
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Input/Output Descriptions and Logic Symbol
Table 3.1 identifies the input and output package connections provided on the device.
Table 3.1
Symbol Amax - A0 DQ15 - DQ0 OE# WE# VSS NC RDY CLK Address Inputs Data Inputs/Outputs Output Enable input Write Enable input Ground
Input/Output Descriptions
Description
(Common)
No Connect; not connected internally. Ready output. Indicates the status of the Burst read. Clock input. In burst mode, after the initial word is output, subsequent active edges of CLK increment the internal address counter. Should be at VIL or VIH while in asynchronous mode. Address Valid input. Indicates to device that the valid address is present on the address inputs. Hardware reset input. Hardware write protect input. At VIL, disables program and erase functions in the four outermost sectors. Should be at VIH for all other conditions. Accelerated input. At VHH, accelerates programming; automatically places device in unlock bypass mode. At VIL, disables all program and erase functions. Should be at VIH for all other conditions. Chip-enable input for pSRAM Chip-enable input for Flash. Chip-enable input for Flash 1. Chip-enable input for Flash 2. Chip-enable input for Flash 3. Control Register Enable . Flash 1.8 Volt-only single power supply. pSRAM Power Supply. Upper Byte Control. Lower Byte Control . (pSRAM) (pSRAM - CellularRAM only) Asynchronous relative to CLK for Burst Mode. (Flash) (Flash) (Common)
AVD# F-RST# F-WP#
F-ACC
R-CE# F-CE# F1-CE# F2-CE# F3-CE# R-CRE F-VCC R-VCC R-UB# R-LB#
Amax - A0 DQ15 - DQ0 CLK CE# F-WP F-ACC F-CE# R-CE# OE# WE# RDY F-RST# AVD# R-UB# R-LB# R-CRE (See Note)
16
Note: R-CRE is only present in CellularRAM-compatible pSRAM.
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MCP Block Diagram
VCCf Flash-only Address Shared Address CLK WP# ACC (Note 2)-- CE#f1 OE# WE# RESET# AVD#
(Note 2)-- CE#f2 (Note 2)-- CE#f3 VCCs
VCC Amax - A0
VID
16
DQ15 - DQ0 CLK WP# ACC CE# OE# WE# RESET# AVD# Flash 1 Flash 2 Flash 3 (Note 3)
DQ15 - DQ0
RDY
RDY VSS
VCC Amax - A0
VCCQ
16
I/O15 - I/O0 CLK CE#s UB#s LB#s CREs CE# WE# OE# UB# LB# AVD# CRE
pSRAM
VSSQ
Notes:
1. 2. 3. CREs is only present in CellularRAM-compatible pSRAM. CE#f1, CE#f2, and CE#f3 are the chip enable pins for the first, second, and third Flash devices, respectively. CE#f3 may not be needed depending on the package. If necessary.
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5.1
Connection Diagrams/Physical Dimensions
This section contains the I/O designations and package specifications for the S75WS.
Special Handling Instructions for FBGA Package
Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150C for prolonged periods of time.
5.2
Connection Diagram - Cellular Ram-Based Pinout, 9 x 12 mm
Legend:
A1
DNU
A10
DNU
X
RFU
B2
ADV#
B3
RFU
B4
CLK
B5
RFU
B6
F-VCC
B7
RFU
B8
RFU
B9
RFU
X
DNU
C2
F1-WP#
C3
A7
C4
R-LB#
C5
F-ACC
C6
WE#
C7
A8
C8
A11
C9
F2-CE#
X
All Shared
D2
A3
D3
A6
D4
R-UB#
D5
F-RST#
D6
RFU
D7
A19
D8
A12
D9
A15
X
MirrorBitTM Data Flash Only
E2
A2
E3
A5
E4
A18
E5
RDY
E6
A20
E7
A9
E8
A13
E9
A21
X
Code Flash Only
F2
A1
F3
A4
F4
A17
F5
RFU
F5
A23
F7
A10
F8
A14
F9
A22
X
RAM Only
G2
A0
G3
VSS
G4
DQ1
G5
RFU
G6
RFU
G7
DQ6
G8
A24
G9
A16
X
Flash Shared Only
H2
F-CE#
H3
OE#
H4
DQ9
H5
DQ3
H6
DQ4
H7
DQ13
H8
DQ15
H9
R-CRE
J2
R-CE1#
J3
DQ0
J4
DQ10
J5
F-VCC
J6
R-VCC
J7
DQ12
J8
DQ7
J9
VSS
K2
RFU
K3
DQ8
K4
DQ2
K5
DQ11
K6
A25
K7
DQ5
K8
DQ14
K9
RFU
L2
RFU
L3
RFU
L4
RFU
L5
F-VCC
L6
RFU
L7
RFU
L8
RFU
L9
RFU
M1
DNU
M10
DNU
Figure 5.1
Connection Diagram - Cellular Ram-Based 84-ball Fine-Pitch Ball Grid Array
5.3
Physical Dimensions
5.3.1 Physical Dimensions - xxx084 - Fine Pitch Ball Grid Array 9 x 12 mm
TBD
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5.4
Look-Ahead Connection Diagram
Look Ahead Pinout - 1.8 V only x 16NOR + x16pSRAM + x16MirrorBit Data
A1 RFU
B1
A2
A9
A10
Legend: RFU
B2
RFU
B9
RFU
B10
X
RFU (Reserved for Future Use)
RFU
RFU
RFU
RFU
C2 AVD# D2 WP# E2 A3 F2 A2 G2
A1
C3 VSS D3 A7 E3 A6 F3 A5 G3
A4
C4 CLK D4 R-LB# D4 R-UB# F4 A18 G4
A17
C5 F2-CE# D5 ACC C7 F-RST# F5 RDY/WAIT# G5
R2-CE1
C6 F-VCC D6 WE# E6 R1-CE2 F6 A20 G6
A23
C7 F-CLK# D7 A8 E7 A19 F7 A9 G7
A10
C8 R-OE# D8 A11 E8 A12 F8 A13 G8
A14
C9 F2-OE# D9 F3-CE# E9 A15 F9 A21 G9
A22
X
Code Flash Only
X
MirrorBit Data Only
X
Flash/Data Shared
H2 A0 J2 F1-CE# K2 R1-CE1# L2 R-VCC M2 A27
H3 VSS J3 OE# K3 DQ0 L3 DQ8 M3 A26
H4 DQ1 J4 DQ9 K4 DQ10 L4 DQ2 M4 VSS
H5 R2-VCC J5 DQ3 K5 F-VCC L5 DQ11 M5 F-VCC
H6 R2-CE2 J6 DQ4 E6 R1-VCC L6 A25 M6 F4-CE#
H7 DQ6 J7 DQ13 K7 DQ12 L7 DQ5 M7 R-VCCQ
H8 A24 J8 DQ15 K8 DQ7 L8 DQ14 M8 F-VCCQ
H9 A16 J9 R-CRE or R-MRS K9 VSS L9 WP# M9 R-CLK#
N9 RFU P9 RFU
X
Flash/xRAM Shared
X
pSRAM Only
X
xRAM Shared
N1
F-DQS0 P1 RFU
N1
N2 RFU P2 RFU
N10
F-DQS1 P10 RFU
Notes:
1. 2. F1 and F2 denote XIP/Code Flash, while F3 and F4 denote Data/Companion Flash In addition to being defined as F2-CE#, Ball C5 can also be assigned as F1-CE2# for code that has two chip enable signals.
Figure 5.2
Look Ahead Pinout - 1.8 V only x 16NOR + x16pSRAM + x16MirrorBit Data
To provide customers with a migration path to higher densities, as well as the option to stack more die in a package, Spansion has prepared a standard pinout that supports: NOR Flash and SRAM densities up to 4 Gigabits NOR Flash and PSRAM densities up to 4 Gigabits NOR Flash and PSRAM and DATA STORAGE densities up to 4 Gigabits The signal locations of the resultant MCP device are shown above. Note that for different densities, the actual package outline may vary. However, any pinout in any MCP will be a subset of the pinout above.
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In some cases, there may be outrigger balls in locations outside the grid shown above. In such cases, the user is recommended to treat these as RFUs, and not connect them to any other signal. In case of any further inquiries about the above look-ahead pinout, please refer to the application note on this subject, or contact your Spansion or Fujitsu sales office.
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S75WS-N MirrorBitTM Flash Family
S29WS256N, S29WS128N, S29WS064N 256/128/64 Megabit (16/8/4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
Data Sheet
PRELIMINARY
General Description
The Spansion S29WS256/128/064N are MirrorbitTM Flash products fabricated on 110 nm process technology. These burst mode Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate banks using separate data and address pins. These products can operate up to 80 MHz and use a single VCC of 1.7 V to 1.95 V that makes them ideal for today's demanding wireless applications requiring higher density, better performance and lowered power consumption.
Distinctive Characteristics
Single 1.8 V read/program/erase (1.70-1.95 V) 110 nm MirrorBitTM Technology Simultaneous Read/Write operation with zero latency 32-word Write Buffer Sixteen-bank architecture consisting of 16/8/4 Mwords for WS256N/128N/064N, respectively Four 16 Kword sectors at both top and bottom of memory array 254/126/62 64 Kword sectors (WS256N/128N/ 064N) Programmable burst read modes -- Linear for 32, 16 or 8 words linear read with or without wrap-around -- Continuous sequential read mode Secured Silicon Sector region consisting of 128 words each for factory and customer 20-year data retention (typical) Cycling Endurance: 100,000 cycles per sector (typical) RDY output indicates data available to system Command set compatible with JEDEC (42.4) standard Hardware (WP#) protection of top and bottom sectors Dual boot sector configuration (top and bottom) Offered Packages -- WS064N: 80-ball FBGA (7 mm x 9 mm) -- WS256N/128N: 84-ball FBGA (8 mm x 11.6 mm) Low VCC write inhibit Persistent and Password methods of Advanced Sector Protection Write operation status bits indicate program and erase operation completion Suspend and Resume commands for Program and Erase operations Unlock Bypass program command to reduce programming time Synchronous or Asynchronous program operation, independent of burst control register settings ACC input pin to reduce factory programming time Support for Common Flash Interface (CFI) Industrial Temperature range (contact factory)
Performance Characteristics
Read Access Times
Speed Option (MHz) Max. Synch. Latency, ns (tIACC) Max. Synch. Burst Access, ns (tBACC) Max. Asynch. Access Time, ns (tACC) Max CE# Access Time, ns (tCE) Max OE# Access Time, ns (tOE) 80 80 9 80 80 13.5 66 80 11.2 80 80 13.5
Current Consumption (typical values)
54 80 13.5 80 80 13.5 Continuous Burst Read @ 66 MHz Simultaneous Operation (asynchronous) Program (asynchronous) Erase (asynchronous) Standby Mode (asynchronous) 35 mA 50 mA 19 mA 19 mA 20 A
Typical Program & Erase Times
Single Word Programming Effective Write Buffer Programming (VCC) Per Word Effective Write Buffer Programming (VACC) Per Word Sector Erase (16 Kword Sector) Sector Erase (64 Kword Sector) 40 s 9.4 s 6 s 150 ms 600 ms
Publication Number S75WS-N-00
Revision A
Amendment 0
Issue Date February 17, 2005
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Additional Resources
Visit www.amd.com and www.fujitsu.com to obtain the following related documents:
Application Notes
Using the Operation Status Bits in AMD Devices Understanding Burst Mode Flash Memory Devices Simultaneous Read/Write vs. Erase Suspend/Resume MirrorBitTM Flash Memory Write Buffer Programming and Page Buffer Read Design-In Scalable Wireless Solutions with Spansion Products Common Flash Interface Version 1.4 Vendor Specific Extensions
Specification Bulletins
Contact your local sales office for details.
Drivers and Software Support
Spansion low-level drivers Enhanced Flash drivers Flash file system
CAD Modeling Support
VHDL and Verilog IBIS ORCAD
Technical Support
Contact your local sales office or contact Spansion LLC directly for additional technical support: Email US and Canada: HW.support@amd.com Asia Pacific: asia.support@amd.com Europe, Middle East, and Africa Japan: http://edevice.fujitsu.com/jp/support/tech/#b7 Frequently Asked Questions (FAQ) http://ask.amd.com/ http://edevice.fujitsu.com/jp/support/tech/#b7 Phone US: (408) 749-5703 Japan (03) 5322-3324
Spansion LLC Locations
915 DeGuigne Drive, P.O. Box 3453 Sunnyvale, CA 94088-3453, USA Telephone: 408-962-2500 or 1-866-SPANSION Spansion Japan Limited 4-33-4 Nishi Shinjuku, Shinjuku-ku Tokyo, 160-0023 Telephone: +81-3-5302-2200 Facsimile: +81-3-5302-2674 http://www.spansion.com
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Product Overview
The S29WS-N family consists of 256, 128 and 64Mbit, 1.8 volts-only, simultaneous read/write burst mode Flash device optimized for today's wireless designs that demand a large storage array, rich functionality, and low power consumption. These devices are organized in 16, 8 or 4 Mwords of 16 bits each and are capable of continuous, synchronous (burst) read or linear read (8-, 16-, or 32-word aligned group) with or without wrap around. These products also offer single word programming or a 32-word buffer for programming with program/erase and suspend functionality. Additional features include: Advanced Sector Protection methods for protecting sectors as required 256 words of Secured Silicon area for storing customer and factory secured information. The Secured Silicon Sector is One Time Programmable.
7.1
Memory Map
The S29WS256/128/064N Mbit devices consist of 16 banks organized as shown in Tables Table 7.1, Table 7.2, and Table 7.3.
Table 7.1 S29WS256N Sector & Memory Address Map
Bank Size Sector Count Sector Size (KB) Bank Sector/ Sector Range SA000 4 32 SA001 0 SA002 SA003 15 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 16 16 16 16 16 16 16 16 16 16 16 16 16 16 15 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SA004 to SA018 SA019 to SA034 SA035 to SA050 SA051 to SA066 SA067 to SA082 SA083 to SA098 SA099 to SA114 SA115 to SA130 SA131 to SA146 SA147 to SA162 SA163 to SA178 SA179 to SA194 SA195 to SA210 SA211 to SA226 SA227 to SA242 SA243 to SA257 SA258 2 MB 4 32 15 SA259 SA260 SA261 Address Range 000000h-003FFFh 004000h-007FFFh 008000h-00BFFFh 00C000h-00FFFFh 010000h-01FFFFh to 0F0000h-0FFFFFh 100000h-10FFFFh to 1F0000h-1FFFFFh 200000h-20FFFFh to 2F0000h-2FFFFFh 300000h-30FFFFh to 3F0000h-3FFFFFh 400000h-40FFFFh to 4F0000h-4FFFFFh 500000h-50FFFFh to 5F0000h-5FFFFFh 600000h-60FFFFh to 6F0000h-6FFFFFh 700000h-70FFFFh to 7F0000h-7FFFFFh 800000h-80FFFFh to 8F0000h-8FFFFFh 900000h-90FFFFh to 9F0000h-9FFFFFh A00000h-A0FFFFh to AF0000h-AFFFFFh B00000h-B0FFFFh to BF0000h-BFFFFFh C00000h-C0FFFFh to CF0000h-CFFFFFh D00000h-D0FFFFh to DF0000h-DFFFFFh E00000h-E0FFFFh to EF0000h-EFFFFFh F00000h-F0FFFFh to FE0000h-FEFFFFh FF0000h-FF3FFFh FF4000h-FF7FFFh FF8000h-FFBFFFh FFC000h-FFFFFFh Contains four smaller sectors at top of addressable memory. All 128 KB sectors. Pattern for sector address range is xx0000h-xxFFFFh. (see note) Contains four smaller sectors at bottom of addressable memory. Notes
2 MB
Note: This table has been condensed to show sector-related information for an entire device on a single page.
Sectors and their address ranges that are not explicitly listed (such as SA005-SA017) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 KB sectors have the pattern xx00000h-xxFFFFh.
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Table 7.2
Bank Size Sector Count Sector Size (KB) 32 4 32 32 32 7 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 8 8 8 8 8 8 8 8 8 8 8 8 8 8 7 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 32 1 MB 4 32 32 32 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 Bank
S29WS128N Sector & Memory Address Map
Sector/ Sector Range SA000 SA001 SA002 SA003 SA004 to SA010 SA011 to SA018 SA019 to SA026 SA027 to SA034 SA035 to SA042 SA043 to SA050 SA051 to SA058 SA059 to SA066 SA067 to SA074 SA075 to SA082 SA083 to SA090 SA091 to SA098 SA099 to SA106 SA107 to SA114 SA115 to SA122 SA123 to SA129 SA130 SA131 SA132 SA133 Address Range 000000h-003FFFh 004000h-007FFFh 008000h-00BFFFh 00C000h-00FFFFh 010000h-01FFFFh to 070000h-07FFFFh 080000h-08FFFFh to 0F0000h-0FFFFFh 100000h-10FFFFh to 170000h-17FFFFh 180000h-18FFFFh to 1F0000h-1FFFFFh 200000h-20FFFFh to 270000h-27FFFFh 280000h-28FFFFh to 2F0000h-2FFFFFh 300000h-30FFFFh to 370000h-37FFFFh 380000h-38FFFFh to 3F0000h-3FFFFFh 400000h-40FFFFh to 470000h-47FFFFh 480000h-48FFFFh to 4F0000h-4FFFFFh 500000h-50FFFFh to 570000h-57FFFFh 580000h-58FFFFh to 5F0000h-5FFFFFh 600000h-60FFFFh to 670000h-67FFFFh 680000h-68FFFFh to 6F0000h-6FFFFFh 700000h-70FFFFh to 770000h-77FFFFh 780000h-78FFFFh to 7E0000h-7EFFFFh 7F0000h-7F3FFFh 7F4000h-7F7FFFh 7F8000h-7FBFFFh 7FC000h-7FFFFFh Contains four smaller sectors at top of addressable memory. All 128 KB sectors. Pattern for sector address range is xx0000h-xxFFFFh. (See Note) Contains four smaller sectors at bottom of addressable memory. Notes
1 MB
Note: This table has been condensed to show sector-related information for an entire device on a single page.
Sectors and their address ranges that are not explicitly listed (such as SA005-SA009) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 KB sectors have the pattern xx00000h-xxFFFFh.
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Table 7.3
Bank Size Sector Count Sector Size (KB) Bank
S29WS064N Sector & Memory Address Map
Sector/ Sector Range SA000 Address Range 000000h-003FFFh 004000h-007FFFh 008000h-00BFFFh 00C000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh to 070000h-07FFFFh 080000h-08FFFFh to 0B0000h-0BFFFFh 0C0000h-0CFFFFh to 0F0000h-0FFFFFh 100000h-10FFFFh to 130000h-13FFFFh 140000h-14FFFFh to 170000h-17FFFFh 180000h-18FFFFh to 1B0000h-1BFFFFh 1C0000h-1CFFFFh to 1F0000h-1FFFFFh 200000h-20FFFFh to 230000h-23FFFFh 240000h-24FFFFh to 270000h-27FFFFh 280000h-28FFFFh to 2B0000h-2BFFFFh 2C0000h-2CFFFFh to 2F0000h-2FFFFFh 300000h-30FFFFh to 330000h-33FFFFh 340000h-34FFFFh to 370000h-37FFFFh 380000h-38FFFFh to 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 3E0000h-3EFFFFh 3F0000h-3F3FFFh 3F4000h-3F7FFFh 3F8000h-3FBFFFh 3FC000h-3FFFFFh Contains four smaller sectors a t top of addressable memory. All 128 KB sectors. Pattern for sector address range is xx0000h-xxFFFFh. (see note) Contains four smaller sectors at bottom of addressable memory. Notes
4 0.5 MB
32 0
SA001 SA002 SA003 SA004
3
128
SA005 SA006
0.5 MB 0.5 MB 0.5 MB 0.5 MB 0.5 MB 0.5 MB 0.5 MB 0.5 MB 0.5 MB 0.5 MB 0.5 MB 0.5 MB 0.5 MB 0.5 MB
4 4 4 4 4 4 4 4 4 4 4 4 4 4
128 128 128 128 128 128 128 128 128 128 128 128 128 128
1 2 3 4 5 6 7 8 9 10 11 12 13 14
SA007-SA010 SA011-SA014 SA015-SA018 SA019-SA022 SA023-SA026 SA027-SA030 SA031-SA034 SA035-SA038 SA039-SA042 SA043-SA046 SA047-SA050 SA051-SA054 SA055-SA058 SA059-SA062 SA063
3
128
SA064 SA065
0.5 MB 4 32
15
SA066 SA067 SA068 SA069
Note: This table has been condensed to show sector-related information for an entire device on a single page.
Sectors and their address ranges that are not explicitly listed (such as SA008-SA009) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 KB sectors have the pattern xx00000h-xxFFFFh.
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8
Device Operations
This section describes the read, program, erase, simultaneous read/write operations, handshaking, and reset features of the Flash devices. Operations are initiated by writing specific commands or a sequence with specific address and data patterns into the command registers (see Table 13.1 and Table 13.2). The command register itself does not occupy any addressable memory location; rather, it is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as input to the internal state machine and the state machine outputs dictate the function of the device. Writing incorrect address and data values or writing them in an improper sequence may place the device in an unknown state, in which case the system must write the reset command to return the device to the reading array data mode.
8.1
Device Operation Table
The device must be setup appropriately for each operation. Table 8.1 describes the required state of each control pin for any particular operation.
Table 8.1
Operation Asynchronous Read - Addresses Latched Asynchronous Read - Addresses Steady State Asynchronous Write Synchronous Write Standby (CE#) Hardware Reset Burst Read Operations (Synchronous) Load Starting Burst Address Advance Burst to next address with appropriate Data presented on the Data Bus Terminate current Burst read cycle Terminate current Burst read cycle via RESET# Terminate current Burst read cycle and start new Burst read cycle L L H X L CE# L L L L H X
Device Operations
OE# L L H H X X WE# H H L L X X Addresses Addr In Addr In Addr In Addr In X X DQ15-0 Data Out Data Out I/O I/O HIGH Z HIGH Z RESET# H H H H H L X X X X CLK X X X L L AVD#
X L X X X
H H H H H
Addr In X X X Addr In
X Burst Data Out HIGH Z HIGH Z I/O
H H H L H X H X X
Legend: L = Logic 0, H = Logic 1, X = Don't Care, I/O = Input/Output.
8.2
Asynchronous Read
All memories require access time to output array data. In an asynchronous read operation, data is read from one memory location at a time. Addresses are presented to the device in random order, and the propagation delay through the device causes the data on its outputs to arrive asynchronously with the address on its inputs. The device defaults to reading array data asynchronously after device power-up or hardware reset. Asynchronous read requires that the CLK signal remain at VIL during the entire memory read operation. To read data from the memory array, the system must first assert a valid address on Amax-A0, while driving AVD# and CE# to VIL. WE# must remain at VIH. The rising edge of AVD# latches the address. The OE# signal must be driven to VIL, once AVD# has been driven to VIH. Data is output on A/DQ15-A/DQ0 pins after the access time (tOE) has elapsed from the falling edge of OE#.
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8.3
Synchronous (Burst) Read Mode and Configuration Register
When a series of adjacent addresses needs to be read from the device (in order from lowest to highest address), the synchronous (or burst read) mode can be used to significantly reduce the overall time needed for the device to output array data. After an initial access time required for the data from the first address location, subsequent data is output synchronized to a clock input provided by the system. The device offers both continuous and linear methods of burst read operation, which are discussed in sections 8.3.1, 8.3.2, and 8.3.3. Since the device defaults to asynchronous read mode after power-up or a hardware reset, the configuration register must be set to enable the burst read mode. Other Configuration Register settings include the number of wait states to insert before the initial word (tIACC) of each burst access, the burst mode in which to operate, and when RDY indicates data is ready to be read. Prior to entering the burst mode, the system should first determine the configuration register settings (and read the current register settings if desired via the Read Configuration Register command sequence), and then write the configuration register command sequence. See 8.3.4 and Table 13.1 for further details.
Power-up/ Hardware Reset
Asynchronous Read Mode Only
Set Burst Mode Configuration Register Command for Synchronous Mode (CR15 = 0)
Set Burst Mode Configuration Register Command for Asynchronous Mode (CR15 = 1)
Synchronous Read Mode Only
Figure 8.1
Synchronous/Asynchronous State Diagram
The device outputs the initial word subject to the following operational conditions: tIACC specification: the time from the rising edge of the first clock cycle after addresses are latched to valid data on the device outputs. Configuration register setting CR13-CR11: the total number of clock cycles (wait states) that occur before valid data appears on the device outputs. The effect is that tIACC is lengthened. The device outputs subsequent words tBACC after the active edge of each successive clock cycle, which also increments the internal address counter. The device outputs burst data at this rate subject to the following operational conditions:
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Starting address: whether the address is divisible by four (where A[1:0] is 00). A divisibleby-four address incurs the least number of additional wait states that occur after the initial word. The number of additional wait states required increases for burst operations in which the starting address is one, two, or three locations above the divisible-by-four address (i.e., where A[1:0] is 01, 10, or 11). Boundary crossing: There is a boundary at every 128 words due to the internal architecture of the device. One additional wait state must be inserted when crossing this boundary if the memory bus is operating at a high clock frequency. Please refer to the tables below. Clock frequency: the speed at which the device is expected to burst data. Higher speeds require additional wait states after the initial word for proper operation. In all cases, with or without latency, the RDY output indicates when the next data is available to be read. Tables 8.2 - 8.6 reflect wait states required for S29WS256/128/064N devices. Refer to the Configuration Register table (CR11 - CR14) and timing diagrams for more details.
Table 8.2
Word 0 1 2 3 Wait States x ws x ws x ws x ws D0 D1 D2 D3 D1 D2 D3 1 ws
Address Latency (S29WS256N)
Cycle D2 D3 1 ws 1 ws D3 1 ws 1 ws 1 ws D4 D4 D4 D4 D5 D5 D5 D5 D6 D6 D6 D6 D7 D7 D7 D7 D8 D8 D8 D8
Table 8.3
Word 0 1 2 3 Wait States 5, 6, 7 ws 5, 6, 7 ws 5, 6, 7 ws 5, 6, 7 ws D0 D1 D2 D3
Address Latency (S29WS128N/S29WS064N)
Cycle D1 D2 D3 1 ws D2 D3 1 ws 1 ws D3 1 ws 1 ws 1 ws D4 D4 D4 D4 D5 D5 D5 D5 D6 D6 D6 D6 D7 D7 D7 D7 D8 D8 D8 D8
Table 8.4
Word 0 1 2 3 7, 6 ws 7, 6 ws 7, 6 ws 7, 6 ws
Address/Boundary Crossing Latency (S29WS256N @ 80/66 MHz)
Cycle D0 D1 D2 D3 D1 D2 D3 1 ws D2 D3 1 ws 1 ws D3 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D4 D4 D4 D4 D5 D5 D5 D5 D6 D6 D6 D6 D7 D7 D7 D7
Wait States
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Table 8.5
Word 0 1 2 3 Wait States 5 ws 5 ws 5 ws 5 ws
Address/Boundary Crossing Latency (S29WS256N @ 54MHz)
Cycle D0 D1 D2 D3 D1 D2 D3 1 ws D2 D3 1 ws 1 ws D3 1 ws 1 ws 1 ws D4 D4 D4 D4 D5 D5 D5 D5 D6 D6 D6 D6 D7 D7 D7 D7 D8 D8 D8 D8
Table 8.6
Word 0 1 2 3 Wait States 5, 6, 7 ws 5, 6, 7 ws 5, 6, 7 ws 5, 6, 7 ws
Address/Boundary Crossing Latency (S29WS128N/S29WS064N)
Cycle D0 D1 D2 D3 D1 D2 D3 1 ws D2 D3 1 ws 1 ws D3 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D4 D4 D4 D4 D5 D5 D5 D5 D6 D6 D6 D6 D7 D7 D7 D7
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Note: Setup Configuration Register parameters
Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h
Unlock Cycle 1 Unlock Cycle 2
Write Set Configuration Register Command and Settings: Address 555h, Data D0h Address X00h, Data CR
Command Cycle CR = Configuration Register Bits CR15-CR0
Load Initial Address Address = RA
RA = Read Address
Wait tIACC + Programmable Wait State Setting
CR13-CR11 sets initial access time (from address latched to valid data) from 2 to 7 clock cycles
Read Initial Data RD = DQ[15:0]
RD = Read Data
Wait X Clocks: Additional Latency Due to Starting Address, Clock Frequency, and Boundary Crossing
Read Next Data RD = DQ[15:0]
Delay X Clocks Crossing Boundary? No
Yes
End of Data?
Yes
Completed
Figure 8.2 Synchronous Read 8.3.1 Continuous Burst Read Mode
In the continuous burst read mode, the device outputs sequential burst data from the starting address given and then wrap around to address 000000h when it reaches the highest addressable memory location. The burst read mode continues until the system drives CE# high, or RESET= VIL. Continuous burst mode can also be aborted by asserting AVD# low and providing a new address to the device. If the address being read crosses a 128-word line boundary (as mentioned above) and the subsequent word line is not being programmed or erased, additional latency cycles are required as reflected by the configuration register table (Table 8.8). If the address crosses a bank boundary while the subsequent bank is programming or erasing, the device provides read status information and the clock is ignored. Upon completion of status read or program or erase operation, the host can restart a burst read operation using a new address and AVD# pulse.
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8.3.2
8-, 16-, 32-Word Linear Burst Read with Wrap Around
In a linear burst read operation, a fixed number of words (8, 16, or 32 words) are read from consecutive addresses that are determined by the group within which the starting address falls. The groups are sized according to the number of words read in a single burst sequence for a given mode (see Table 8.7). For example, if the starting address in the 8-word mode is 3Ch, the address range to be read would be 38-3Fh, and the burst sequence would be 3C-3D-3E-3F-38-39-3A-3Bh. Thus, the device outputs all words in that burst address group until all word are read, regardless of where the starting address occurs in the address group, and then terminates the burst read. In a similar fashion, the 16-word and 32-word Linear Wrap modes begin their burst sequence on the starting address provided to the device, then wrap back to the first address in the selected address group. Note that in this mode the address pointer does not cross the boundary that occurs every 128 words; thus, no additional wait states are inserted due to boundary crossing.
Table 8.7
Mode 8-word 16-word 32-word Group Size 8 words 16 words 32 words
Burst Address Groups
Group Address Ranges 0-7h, 8-Fh, 10-17h,... 0-Fh, 10-1Fh, 20-2Fh,... 00-1Fh, 20-3Fh, 40-5Fh,...
8.3.3
8-, 16-, 32-Word Linear Burst without Wrap Around
If wrap around is not enabled for linear burst read operations, the 8-word, 16-word, or 32-word burst executes up to the maximum memory address of the selected number of words. The burst stops after 8, 16, or 32 addresses and does not wrap around to the first address of the selected group. For example, if the starting address in the 8- word mode is 3Ch, the address range to be read would be 39-40h, and the burst sequence would be 3C-3D-3E-3F-40-41-42-43h if wrap around is not enabled. The next address to be read requires a new address and AVD# pulse. Note that in this burst read mode, the address pointer may cross the boundary that occurs every 128 words, which will incur the additional boundary crossing wait state.
8.3.4
Configuration Register
The configuration register sets various operational parameters associated with burst mode. Upon power-up or hardware reset, the device defaults to the asynchronous read mode, and the configuration register settings are in their default state. The host system should determine the proper settings for the entire configuration register, and then execute the Set Configuration Register command sequence, before attempting burst operations. The configuration register is not reset after deasserting CE#. The Configuration Register can also be read using a command sequence (see Table 13.1). The following list describes the register settings.
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Table 8.8
CR Bit CR15 Function Set Device Read Mode
Configuration Register
Settings (Binary) 0 = Synchronous Read (Burst Mode) Enabled 1 = Asynchronous Read Mode (default) Enabled
54 MHz 66 Mhz 80 MHz CR14 Boundary Crossing S29WS064N S29WS128N S29WS256N S29WS064N S29WS128N S29WS256N CR12 Programmable Wait State S29WS064N S29WS128N S29WS256N S29WS064N S29WS128N S29WS256N CR10 CR9 CR8 CR7 CR6 CR5 CR4 CR3 RDY Polarity Reserved RDY Reserved Reserved Reserved Reserved Burst Wrap Around 1 0 1 1 0 0 N/A N/A N/A Default value is 0 0 = No extra boundary crossing latency 1 = With extra boundary crossing latency (default) Must be set to 1 greater than 54 MHz. 011 = Data valid on 5th active CLK edge after addresses latched 100 = Data valid on 6th active CLK edge after addresses latched 101 = Data valid on 7th active CLK edge after addresses latched (default) 110 = Reserved 111 = Reserved Inserts wait states before initial data is available. Setting greater number of wait states before initial data reduces latency after initial data. (Notes 1, 2) 0 = RDY signal active low 1 = RDY signal active high (default) 1 = default 0 = RDY active one clock cycle before data 1 = RDY active with data (default) When CR13-CR11 are set to 000, RDY is active with data regardless of CR8 setting. 1 = default 1 = default 0 = default 0 = default 0 = No Wrap Around Burst 1 = Wrap Around Burst (default) 000 = Continuous (default) 010 = 8-Word Linear Burst 011 = 16-Word Linear Burst 100 = 32-Word Linear Burst (All other bit settings are reserved)
0
1
1
CR13
0
1
1
CR11
CR2 CR1 CR0
Burst Length
Notes:
1. 2. 3. Refer to Tables 8.2 - 8.6 for wait states requirements. Refer to Synchronous Burst Read timing diagrams Configuration Register is in the default state upon power-up or hardware reset.
Reading the Configuration Table. The configuration register can be read with a four-cycle command sequence. See Table 13.1 for sequence details. Once the data has been read from the configuration register, a software reset command is required to set the device into the correct state.
8.4
Autoselect
The Autoselect is used for manufacturer ID, Device identification, and sector protection information. This mode is primarily intended for programming equipment to automatically match a device with its corresponding programming algorithm. The Autoselect codes can also be accessed in-system. When verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Table 8.9). The remaining address bits are don't care. The most significant four bits of the address during the third write cycle selects the bank from which the Autoselect codes are read by the host. All other banks can be accessed normally for data read without exiting the Autoselect mode. To access the Autoselect codes, the host system must issue the Autoselect command.
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The Autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The Autoselect command may not be written while the device is actively programming or erasing. Autoselect does not support simultaneous operations or burst mode. The system must write the reset command to return to the read mode (or erase-suspendread mode if the bank was previously in Erase Suspend). See Table 13.1 for command sequence details.
Table 8.9
Description Manufacturer ID Device ID, Word 1 Device ID, Word 2 Device ID, Word 3 Address (BA) + 00h (BA) + 01h (BA) + 0Eh (BA) + 0Fh 0001h 227Eh
Autoselect Addresses
Read Data
2230 (WS256N) 2231 (WS128N) 2232 (WS064N) 2200 DQ15 - DQ8 = Reserved DQ7 (Factory Lock Bit): 1 = Locked, 0 = Not Locked DQ6 (Customer Lock Bit): 1 = Locked, 0 = Not Locked DQ5 (Handshake Bit): 1 = Reserved, 0 = Standard Handshake Indicator Bits (See Note) (BA) + 03h DQ4, DQ3 (WP# Protection Boot Code): 00 = WP# Protects both Top Boot and Bottom Boot Sectors. 01, 10, 11 = Reserved DQ2 = Reserved DQ1 (DYB Power up State [Lock Register DQ4]): 1 = Unlocked (user option), 0 = Locked (default) DQ0 (PPB Eraseability [Lock Register DQ3]): 1 = Erase allowed, 0 = Erase disabled Sector Block Lock/ Unlock (SA) + 02h 0001h = Locked, 0000h = Unlocked
Note: For WS128N and WS064, DQ1 and DQ0 are reserved.
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Software Functions and Sample Code
Table 8.10
Cycle Unlock Cycle 1 Unlock Cycle 2 Autoselect Command Operation Write Write Write
Autoselect Entry
Word Address BAx555h BAx2AAh BAx555h Data 0x00AAh 0x0055h 0x0090h
(LLD Function = lld_AutoselectEntryCmd)
Byte Address BAxAAAh BAx555h BAxAAAh
Table 8.11
Cycle Unlock Cycle 1 Operation Write
Autoselect Exit
Word Address base + XXXh Data 0x00F0h
(LLD Function = lld_AutoselectExitCmd)
Byte Address base + XXXh
Notes: 1. Any offset within the device works. 2. BA = Bank Address. The bank address is required. 3. base = base address.
The following is a C source code example of using the autoselect function to read the manufacturer ID. Refer to the Spansion Low Level Driver User Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines.
/* Here is an example of Autoselect mode (getting manufacturer ID) */ /* Define UINT16 example: typedef unsigned short UINT16; */ UINT16 manuf_id; /* Auto Select Entry */ *( (UINT16 *)bank_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */ *( (UINT16 *)bank_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */ *( (UINT16 *)bank_addr + 0x555 ) = 0x0090; /* write autoselect command */
/* multiple reads can be performed after entry */ manuf_id = *( (UINT16 *)bank_addr + 0x000 ); /* read manuf. id */ /* Autoselect exit */
*( (UINT16 *)base_addr + 0x000 ) = 0x00F0; /* exit autoselect (write reset command) */
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8.5
Program/Erase Operations
These devices are capable of several modes of programming and or erase operations which are described in detail in the following sections. However, prior to any programming and or erase operation, devices must be setup appropriately as outlined in the configuration register (Table 8.8). For any program and or erase operations, including writing command sequences, the system must drive AVD# and CE# to VIL, and OE# to VIH when providing an address to the device, and drive WE# and CE# to VIL, and OE# to VIH when writing commands or programming data. Addresses are latched on the last falling edge of WE# or CE#, while data is latched on the 1st rising edge of WE# or CE#. Note the following: When the Embedded Program algorithm is complete, the device returns to the read mode. The system can determine the status of the program operation by using DQ7 or DQ6. Refer to the Write Operation Status section for information on these status bits. A 0 cannot be programmed back to a 1. Attempting to do so causes the device to set DQ5 = 1 (halting any further operation and requiring a reset command). A succeeding read shows that the data is still 0. Only erase operations can convert a 0 to a 1. Any commands written to the device during the Embedded Program Algorithm are ignored except the Program Suspend command. Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a program operation is in progress. A hardware reset immediately terminates the program operation and the program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries for single word programming operation.
8.5.1
Single Word Programming
Single word programming mode is the simplest method of programming. In this mode, four Flash command write cycles are used to program an individual Flash address. The data for this programming operation could be 8-, 16- or 32-bits wide. While this method is supported by all Spansion devices, in general it is not recommended for devices that support Write Buffer Programming. See Table 13.1 for the required bus cycles and Figure 8.3 for the flowchart. When the Embedded Program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7 or DQ6. Refer to the Write Operation Status section for information on these status bits. During programming, any command (except the Suspend Program command) is ignored. The Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a program operation is in progress. A hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity.
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Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h
Unlock Cycle 1 Unlock Cycle 2
Write Program Command: Address 555h, Data A0h
Setup Command
Program Data to Address: PA, PD
Program Address (PA), Program Data (PD)
Perform Polling Algorithm
(see Write Operation Status flowchart)
Polling Status = Busy? No Yes Polling Status = Done? No
Yes
Error condition (Exceeded Timing Limits)
PASS. Device is in read mode.
FAIL. Issue reset command to return to read array mode.
Figure 8.3
Single Word Program
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Software Functions and Sample Code
Table 8.12
Cycle Unlock Cycle 1 Unlock Cycle 2 Program Setup Program Operation Write Write Write Write
Single Word Program
Byte Address Base + AAAh Base + 554h Base + AAAh Word Address Word Address Base + 555h Base + 2AAh Base + 555h Word Address Data 00AAh 0055h 00A0h Data Word
(LLD Function = lld_ProgramCmd)
Note: Base = Base Address.
The following is a C source code example of using the single word program function. Refer to the Spansion Low Level Driver User's Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Program Command */ *( (UINT16 *)base_addr + 0x555 ) *( (UINT16 *)base_addr + 0x2AA ) *( (UINT16 *)base_addr + 0x555 ) *( (UINT16 *)pa ) /* Poll for program completion */ = = = = 0x00AA; 0x0055; 0x00A0; data; /* /* /* /* write write write write unlock cycle 1 unlock cycle 2 program setup command data to be programmed */ */ */ */
8.5.2
Write Buffer Programming
Write Buffer Programming allows the system to write a maximum of 32 words in one programming operation. This results in a faster effective word programming time than the standard word programming algorithms. The Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the Sector Address in which programming occurs. At this point, the system writes the number of word locations minus 1 that are loaded into the page buffer at the Sector Address in which programming occurs. This tells the device how many write buffer addresses are loaded with data and therefore when to expect the Program Buffer to Flash confirm command. The number of locations to program cannot exceed the size of the write buffer or the operation aborts. (Number loaded = the number of locations to program minus 1. For example, if the system programs 6 address locations, then 05h should be written to the device.) The system then writes the starting address/data combination. This starting address is the first address/data pair to be programmed, and selects the write-buffer-page address. All subsequent address/data pairs must fall within the elected-write-buffer-page. The write-buffer-page is selected by using the addresses AMAX - A5. The write-buffer-page addresses must be the same for all address/data pairs loaded into the write buffer. (This means Write Buffer Programming cannot be performed across multiple write-bufferpages. This also means that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load programming data outside of the selected write-buffer-page, the operation ABORTs.) After writing the Starting Address/Data pair, the system then writes the remaining address/data pairs into the write buffer. Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter is decremented for every data load operation. Also, the last data loaded at a location before the Program Buffer to Flash confirm command is programmed into the device. It is the software's responsibility to comprehend ramifications of loading a write-buffer location more than once. The
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counter decrements for each data load operation, NOT for each unique write-buffer-address location. Once the specified number of write buffer locations have been loaded, the system must then write the Program Buffer to Flash command at the Sector Address. Any other address/data write combinations abort the Write Buffer Programming operation. The device goes busy. The Data Bar polling techniques should be used while monitoring the last address location loaded into the write buffer. This eliminates the need to store an address in memory because the system can load the last address location, issue the program confirm command at the last loaded address location, and then data bar poll at that same address. DQ7, DQ6, DQ5, DQ2, and DQ1 should be monitored to determine the device status during Write Buffer Programming. The write-buffer embedded programming operation can be suspended using the standard suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device returns to READ mode. The Write Buffer Programming Sequence is ABORTED under any of the following conditions: Load a value that is greater than the page buffer size during the Number of Locations to Program step. Write to an address in a sector different than the one specified during the Write-Buffer-Load command. Write an Address/Data pair to a different write-buffer-page than the one selected by the Starting Address during the write buffer data loading stage of the operation. Write data other than the Confirm Command after the specified number of data load cycles. The ABORT condition is indicated by DQ1 = 1, DQ7 = Data# (for the last address location loaded), DQ6 = TOGGLE, DQ5 = 0. This indicates that the Write Buffer Programming Operation was ABORTED. A Write-to-Buffer-Abort reset command sequence is required when using the write buffer Programming features in Unlock Bypass mode. Note that the Secured Silicon sector, autoselect, and CFI functions are unavailable when a program operation is in progress. Write buffer programming is allowed in any sequence of memory (or address) locations. These flash devices are capable of handling multiple write buffer programming operations on the same write buffer address range without intervening erases. Use of the write buffer is strongly recommended for programming when multiple words are to be programmed. Write buffer programming is approximately eight times faster than programming one word at a time.
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Software Functions and Sample Code
Table 8.13
Cycle 1 2 3 4 Description Unlock Unlock Write Buffer Load Command Write Word Count
Write Buffer Program
Byte Address Base + AAAh Base + 554h Word Address Base + 555h Base + 2AAh Data 00AAh 0055h 0025h Word Count (N-1)h
(LLD Functions Used = lld_WriteToBufferCmd, lld_ProgramBufferToFlashCmd)
Operation Write Write Write Write
Program Address Program Address
Number of words (N) loaded into the write buffer can be from 1 to 32 words. 5 to 36 Last Load Buffer Word N Write Buffer to Flash Write Write Program Address, Word N Sector Address Word N 0029h
Notes:
1. Base = Base Address. 2. Last = Last cycle of write buffer program operation; depending on number of words written, the total number of cycles may be from 6 to 37.
3. For maximum efficiency, it is recommended that the write buffer be loaded with the highest number of words (N words) possible.
The following is a C source code example of using the write buffer program function. Refer to th e S p a n s i o n L o w L e v el D r i v e r U s e r G u i de ( ava il able o n w w w. a m d. c o m a n d www.fujitsu.comm) for general information on Spansion Flash memory software development guidelines.
/* Example: Write Buffer Programming Command */ /* NOTES: Write buffer programming limited to 16 words. */ /* All addresses to be written to the flash in */ /* one operation must be within the same flash */ /* page. A flash page begins at addresses */ /* evenly divisible by 0x20. */ UINT16 *src = source_of_data; /* address of source data */ UINT16 *dst = destination_of_data; /* flash destination address */ UINT16 wc = words_to_program -1; /* word count (minus 1) */ *( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */ *( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */ *( (UINT16 *)sector_address ) = 0x0025; /* write write buffer load command */ *( (UINT16 *)sector_address ) = wc; /* write word count (minus 1) */ loop: *dst = *src; /* ALL dst MUST BE SAME PAGE */ /* write source data to destination */ dst++; /* increment destination pointer */ src++; /* increment source pointer */ if (wc == 0) goto confirm /* done when word count equals zero */ wc--; /* decrement word count */ goto loop; /* do it again */ confirm: *( (UINT16 *)sector_address ) = 0x0029; /* write confirm command */ /* poll for completion */
/* Example: Write Buffer Abort Reset */ *( (UINT16 *)addr + 0x555 ) = 0x00AA; *( (UINT16 *)addr + 0x2AA ) = 0x0055; *( (UINT16 *)addr + 0x555 ) = 0x00F0;
/* write unlock cycle 1 /* write unlock cycle 2 /* write buffer abort reset
*/ */ */
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Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h
Unlock Cycle 1 Unlock Cycle 2
Issue Write Buffer Load Command: Address 555h, Data 25h
Load Word Count to Program Program Data to Address: SA = wc
wc = number of words - 1
Yes wc = 0?
Confirm command: SA 29h
No Wait 4 s Write Next Word, Decrement wc: PA data , wc = wc - 1 No Write Buffer Abort Desired? Perform Polling Algorithm Yes Write to a Different Sector Address to Cause Write Buffer Abort
(see Write Operation Status flowchart)
Polling Status = Done? No No
Yes
Error?
Yes
Write Buffer Abort? No
Yes
RESET. Issue Write Buffer Abort Reset Command
FAIL. Issue reset command to return to read array mode.
PASS. Device is in read mode.
Figure 8.4 Write Buffer Programming Operation 8.5.3 Sector Erase
The sector erase function erases one or more sectors in the memory array. (See Table 13.1 and Figure 8.5) The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. After a successful sector erase, all locations within the erased sector contain FFFFh. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of no less than tSEA occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than tSEA.
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Any sector erase address and command following the exceeded time-out (tSEA) may or may not be accepted. Any command other than Sector Erase or Erase Suspend during the time-out period resets that bank to the read mode. The system can monitor DQ3 to determine if the sector erase timer has timed out (see DQ3: Sector Erase Timeout State Indicator). The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing banks. The system can determine the status of the erase operation by reading DQ7 or DQ6/DQ2 in the erasing bank. See Write Operation Status for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Figure 8.5 illustrates the algorithm for the erase operation. See Erase/Program Timing for parameters and timing diagrams.
Software Functions and Sample Code
Table 8.14
Cycle 1 2 3 4 5 6 Description Unlock Unlock Setup Command Unlock Unlock Sector Erase Command Operation Write Write Write Write Write Write
Sector Erase
Byte Address Base + AAAh Base + 554h Base + AAAh Base + AAAh Base + 554h Sector Address Word Address Base + 555h Base + 2AAh Base + 555h Base + 555h Base + 2AAh Sector Address Data 00AAh 0055h 0080h 00AAh 0055h 0030h
(LLD Function = lld_SectorEraseCmd)
Unlimited additional sectors may be selected for erase; command(s) must be written within tSEA.
The following is a C source code example of using the sector erase function. Refer to the Spansion Low Level Driver User's Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Sector Erase Command *( (UINT16 *)base_addr + 0x555 *( (UINT16 *)base_addr + 0x2AA *( (UINT16 *)base_addr + 0x555 *( (UINT16 *)base_addr + 0x555 *( (UINT16 *)base_addr + 0x2AA *( (UINT16 *)sector_address ) */ )= )= )= )= )= = 0x00AA; 0x0055; 0x0080; 0x00AA; 0x0055; 0x0030; /* /* /* /* /* /* write write write write write write unlock cycle 1 */ unlock cycle 2 */ setup command */ additional unlock cycle 1 */ additional unlock cycle 2 */ sector erase command */
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Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h
Unlock Cycle 1 Unlock Cycle 2
Write Sector Erase Cycles: Address 555h, Data 80h Address 555h, Data AAh Address 2AAh, Data 55h Sector Address, Data 30h
Command Cycle 1 Command Cycle 2 Command Cycle 3 Specify first sector for erasure
No
Select Additional Sectors? Yes Write Additional Sector Addresses
* Each additional cycle must be written within tSEA timeout * Timeout resets after each additional cycle is written * The host system may monitor DQ3 or wait tSEA to ensure acceptance of erase commands
No
Poll DQ3. DQ3 = 1? Yes
Yes
Last Sector Selected? No
* No limit on number of sectors * Commands other than Erase Suspend or selecting additional sectors for erasure during timeout reset device to reading array data
Wait 4 s
Perform Write Operation Status Algorithm
Status may be obtained by reading DQ7, DQ6 and/or DQ2.
Yes
Done?
No DQ5 = 1? Yes No Error condition (Exceeded Timing Limits)
PASS. Device returns to reading array.
FAIL. Write reset command to return to reading array.
Notes:
1. 2. See Table 13.1 for erase command sequence. See the section on DQ3 for information on the sector erase timeout.
Figure 8.5
Sector Erase Operation
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8.5.4
Chip Erase Command Sequence
Chip erase is a six-bus cycle operation as indicated by Table 13.1. These commands invoke the Embedded Erase algorithm, which does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. After a successful chip erase, all locations of the chip contain FFFFh. The system is not required to provide any controls or timings during these operations. Table 13.1 and Table 13.2 in the appendix show the address and data requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7 or DQ6/DQ2. See Write Operation Status for information on these status bits. Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity.
Software Functions and Sample Code
Table 8.15
Cycle 1 2 3 4 5 6 Description Unlock Unlock Setup Command Unlock Unlock Chip Erase Command Operation Write Write Write Write Write Write
Chip Erase
Byte Address Base + AAAh Base + 554h Base + AAAh Base + AAAh Base + 554h Base + AAAh Word Address Base + 555h Base + 2AAh Base + 555h Base + 555h Base + 2AAh Base + 555h Data 00AAh 0055h 0080h 00AAh 0055h 0010h
(LLD Function = lld_ChipEraseCmd)
The following is a C source code example of using the chip erase function. Refer to the Spansion Low Level Driver User's Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Chip Erase Command */ /* Note: Cannot be suspended */ *( (UINT16 *)base_addr + 0x555 ) *( (UINT16 *)base_addr + 0x2AA ) *( (UINT16 *)base_addr + 0x555 ) *( (UINT16 *)base_addr + 0x555 ) *( (UINT16 *)base_addr + 0x2AA ) *( (UINT16 *)base_addr + 0x000 )
= = = = = =
0x00AA; 0x0055; 0x0080; 0x00AA; 0x0055; 0x0010;
/* /* /* /* /* /*
write write write write write write
unlock cycle 1 */ unlock cycle 2 */ setup command */ additional unlock cycle 1 */ additional unlock cycle 2 */ chip erase command */
8.5.5
Erase Suspend/Erase Resume Commands
When the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. The bank address is required when writing this command. This command is valid only during the sector erase operation, including the minimum tSEA time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation. When the Erase Suspend command is written after the tSEA time-out period has expired and during the sector erase operation, the device requires a maximum of tESL (erase suspend latency) to suspend the erase operation.
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After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device erase suspends all sectors selected for erasure.) Reading at any address within erasesuspended sectors produces status information on DQ7-DQ0. The system can use DQ7, or DQ6, and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to Table 8.23 for information on these status bits. After an erase-suspended program operation is complete, the bank returns to the erase-suspendread mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. In the erase-suspend-read mode, the system can also issue the Autoselect command sequence. See Write Buffer Programming and Autoselect for details. To resume the sector erase operation, the system must write the Erase Resume command. The bank address of the erase-suspended bank is required when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing.
Software Functions and Sample Code
Table 8.16
Cycle 1 Operation Write
Erase Suspend
Word Address Bank Address Data 00B0h
(LLD Function = lld_EraseSuspendCmd)
Byte Address Bank Address
The following is a C source code example of using the erase suspend function. Refer to the Spansion Low Level Driver User's Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Erase suspend command */ *( (UINT16 *)bank_addr + 0x000 ) = 0x00B0; /* write suspend command */
Table 8.17
Cycle 1 Operation Write
Erase Resume
Word Address Bank Address Data 0030h
(LLD Function = lld_EraseResumeCmd)
Byte Address Bank Address
The following is a C source code example of using the erase resume function. Refer to the Spansion Low Level Driver User's Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Erase resume command */ *( (UINT16 *)bank_addr + 0x000 ) = 0x0030; /* write resume command /* The flash needs adequate time in the resume state */ */
8.5.6
Program Suspend/Program Resume Commands
The Program Suspend command allows the system to interrupt an embedded programming operation or a Write to Buffer programming operation so that data can read from any nonsuspended sector. When the Program Suspend command is written during a programming process, the device halts the programming operation within tPSL (program suspend latency) and updates the status bits. Addresses are don't-cares when writing the Program Suspend command.
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After the programming operation has been suspended, the system can read array data from any non-suspended sector. The Program Suspend command may also be issued during a programming operation while an erase is suspended. In this case, data may be read from any addresses not in Erase Suspend or Program Suspend. If a read is needed from the Secured Silicon Sector area, then user must use the proper command sequences to enter and exit this region. The system may also write the Autoselect command sequence when the device is in Program Suspend mode. The device allows reading Autoselect codes in the suspended sectors, since the codes are not stored in the memory array. When the device exits the Autoselect mode, the device reverts to Program Suspend mode, and is ready for another valid operation. See Autoselect for more information. After the Program Resume command is written, the device reverts to programming. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See Write Operation Status for more information. The system must write the Program Resume command (address bits are don't care) to exit the Program Suspend mode and continue the programming operation. Further writes of the Program Resume command are ignored. Another Program Suspend command can be written after the device has resumed programming.
Software Functions and Sample Code
Table 8.18
Cycle 1 Operation Write
Program Suspend
Word Address Bank Address Data 00B0h
(LLD Function = lld_ProgramSuspendCmd)
Byte Address Bank Address
The following is a C source code example of using the program suspend function. Refer to the Spansion Low Level Driver User's Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Program suspend command */ *( (UINT16 *)base_addr + 0x000 ) = 0x00B0; /* write suspend command */
Table 8.19
Cycle 1 Operation Write
Program Resume
Word Address Bank Address Data 0030h
(LLD Function = lld_ProgramResumeCmd)
Byte Address Bank Address
The following is a C source code example of using the program resume function. Refer to the Spansion Low Level Driver User's Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Program resume command */ *( (UINT16 *)base_addr + 0x000 ) = 0x0030; /* write resume command */
8.5.7
Accelerated Program/Chip Erase
Accelerated single word programming, write buffer programming, sector erase, and chip erase operations are enabled through the ACC function. This method is faster than the standard chip program and erase command sequences. The accelerated chip program and erase functions must not be used more than 10 times per sector. In addition, accelerated chip program and erase should be performed at room temperature (25C 10C).
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If the system asserts VHH on this input, the device automatically enters the aforementioned Unlock Bypass mode and uses the higher voltage on the input to reduce the time required for program and erase operations. The system can then use the Write Buffer Load command sequence provided by the Unlock Bypass mode. Note that if a Write-to-Buffer-Abort Reset is required while in Unlock Bypass mode, the full 3-cycle RESET command sequence must be used to reset the device. Removing VHH from the ACC input, upon completion of the embedded program or erase operation, returns the device to normal operation. Sectors must be unlocked prior to raising ACC to VHH. The ACC pin must not be at VHH for operations other than accelerated programming and accelerated chip erase, or device damage may result. The ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. ACC locks all sector if set to VIL. ACC should be set to VIH for all other conditions.
8.5.8
Unlock Bypass
The device features an Unlock Bypass mode to facilitate faster word programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program data, instead of the normal four cycles. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. See the Appendix for the requirements for the unlock bypass command sequences. During the unlock bypass mode, only the Read, Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the bank address and the data 90h. The second cycle need only contain the data 00h. The bank then returns to the read mode.
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Software Functions and Sample Code
The following are C source code examples of using the unlock bypass entry, program, and exit functions. Refer to the Spansion Low Level Driver User's Guide (available soon on www.amd.com and www.fujitsu.com) for general information on Spansion Flash "memory software development guidelines.
Table 8.20
Cycle 1 2 3 Description Unlock Unlock Entry Command
Unlock Bypass Entry
Byte Address Base + AAAh Base + 554h Base + AAAh Word Address Base + 555h Base + 2AAh Base + 555h
*/ */ */
(LLD Function = lld_UnlockBypassEntryCmd)
Operation Write Write Write
Data 00AAh 0055h 0020h
/* Example: Unlock Bypass Entry Command */ *( (UINT16 *)bank_addr + 0x555 ) = 0x00AA; /* write unlock *( (UINT16 *)bank_addr + 0x2AA ) = 0x0055; /* write unlock *( (UINT16 *)bank_addr + 0x555 ) = 0x0020; /* write unlock /* At this point, programming only takes two write cycles. /* Once you enter Unlock Bypass Mode, do a series of like /* operations (programming or sector erase) and then exit /* Unlock Bypass Mode before beginning a different type of /* operations.
cycle 1 cycle 2 bypass command */ */ */ */ */
Table 8.21
Cycle 1 2 Description Program Setup Command Program Command
Unlock Bypass Program
Byte Address Base + xxxh Program Address Word Address Base +xxxh Program Address Data 00A0h Program Data
(LLD Function = lld_UnlockBypassProgramCmd)
Operation Write Write
/* Example: Unlock Bypass Program Command */ /* Do while in Unlock Bypass Entry Mode! */ *( (UINT16 *)bank_addr + 0x555 ) = 0x00A0; *( (UINT16 *)pa ) = data; /* Poll until done or error. */ /* If done and more to program, */ /* do above two cycles again. */
/* write program setup command /* write data to be programmed
*/ */
Table 8.22
Cycle 1 2 Description Reset Cycle 1 Reset Cycle 2
Unlock Bypass Reset
Byte Address Base + xxxh Base + xxxh Word Address Base +xxxh Base +xxxh Data 0090h 0000h
(LLD Function = lld_UnlockBypassResetCmd)
Operation Write Write
/* Example: Unlock Bypass Exit Command */ *( (UINT16 *)base_addr + 0x000 ) = 0x0090; *( (UINT16 *)base_addr + 0x000 ) = 0x0000;
8.5.9
Write Operation Status
The device provides several bits to determine the status of a program or erase operation. The following subsections describe the function of DQ1, DQ2, DQ3, DQ5, DQ6, and DQ7.
DQ7: Data# Polling. The Data# Polling bit, DQ7, indicates to the host system whether an Em-
bedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command se-
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quence. Note that the Data# Polling is valid only for the last word being programmed in the writebuffer-page during Write Buffer Programming. Reading Data# Polling status on any word other than the last word to be programmed in the write-buffer-page returns false status information. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# polling on DQ7 is active for approximately tPSP, then that bank returns to the read mode. During the Embedded Erase Algorithm, Data# polling produces a 0 on DQ7. When the Embedded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a 1 on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately tASP, then the bank returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ6-DQ0 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ6-DQ0 may be still invalid. Valid data on DQ7-D00 appears on successive read cycles. See the following for more information: Table 8.23, Write Operation Status, shows the outputs for Data# Polling on DQ7. Figure 8.6, Write Operation Status Flowchart, shows the Data# Polling algorithm; and Figure 12.17, Data# Polling Timings (During Embedded Algorithm), shows the Data# Polling timing diagram.
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START
Read 1
(Note 6) DQ7=valid data? NO
YES
Erase Operation Complete
Read 1 DQ5=1? NO
YES
Read 2
YES Read3= valid data? NO
YES
Write Buffer Programming?
Read 2
Read 3 Program Operation Failed YES
Programming Operation?
NO Read 3 Device BUSY, Re-Poll
NO (Note 3) (Note 1) DQ6 toggling? YES TIMEOUT (Note 1) DQ6 toggling? NO (Note 2) Device BUSY, Re-Poll Read 2 DQ2 toggling? NO YES DEVICE ERROR (Note 5)
(Note 4) Read3 DQ1=1?
YES
NO
NO
YES
Device BUSY, Re-Poll Erase Operation Complete Device in Erase/Suspend Mode
Read 3
Read3 DQ1=1 AND DQ7 Valid Data?
YES
Write Buffer Operation Failed
NO Notes: 1) DQ6 is toggling if Read2 DQ6 does not equal Read3 DQ6. 2) DQ2 is toggling if Read2 DQ2 does not equal Read3 DQ2. 3) May be due to an attempt to program a 0 to 1. Use the RESET command to exit operation. 4) Write buffer error if DQ1 of last read =1. 5) Invalid state, use RESET command to exit operation. 6) Valid data is the data that is intended to be programmed or all 1's for an erase operation. 7) Data polling algorithm valid for all operations except advanced sector protection.
Device BUSY, Re-Poll
Figure 8.6
Write Operation Status Flowchart
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DQ6: Toggle Bit I . Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address in the same bank, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately tASP [all sectors protected toggle time], then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erasesuspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately tPAP after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program Algorithm is complete. See the following for additional information: Figure 8.6, Write Operation Status Flowchart; Figure 12.18, Toggle Bit Timings (During Embedded Algorithm), and Table 8.23 and Table 8.24. Toggle Bit I on DQ6 requires either OE# or CE# to be de-asserted and reasserted to show the change in state.
DQ2: Toggle Bit II . The Toggle Bit II on DQ2, when used with DQ6, indicates whether a partic-
ular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 8.23 to compare outputs for DQ2 and DQ6. See the following for additional information: Figure 8.6, the DQ6: Toggle Bit I section, and Figures 12.17-12.20.
Reading Toggle Bits DQ6/DQ2. Whenever the system initially begins reading toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erases operation. The system can read array data on DQ7-DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erases operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it
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may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. Refer to Figure 8.6 for more details.
DQ5: Exceeded Timing Limits. DQ5 indicates whether the program or erase time has exceeded
a specified internal pulse count limit. Under these conditions DQ5 produces a 1, indicating that the program or erase cycle was not successfully completed. The device may output a 1 on DQ5 if the system tries to program a 1 to a location that was previously programmed to 0 Only an erase operation can change a 0 back to a 1. Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a 1. Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode).
DQ3: Sector Erase Timeout State Indicator. After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a 0 to a 1. If the time between additional sector erase commands from the system can be assumed to be less than tSEA, the system need not monitor DQ3. See Sector Erase Command Sequence for more details.
After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is 1, the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is 0 the device accepts additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each sub-sequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 8.23 shows the status of DQ3 relative to the other status bits.
DQ1: Write to Buffer Abort. DQ1 indicates whether a Write to Buffer operation was aborted.
Under these conditions DQ1 produces a 1. The system must issue the Write to Buffer Abort Reset command sequence to return the device to reading array data. See Write Buffer Programming Operation for more details.
Table 8.23
Program Suspend Mode (Note 3) Reading within Program Suspended Sector Reading within Non-Program Suspended Sector BUSY State Exceeded Timing Limits ABORT State
Write Operation Status
INVALID (Not Allowed) Data DQ7# DQ7# DQ7# INVALID (Not Allowed) Data Toggle Toggle Toggle INVALID (Not Allowed) Data 0 1 0 INVALID (Not Allowed) Data N/A N/A N/A INVALID (Not Allowed) Data N/A N/A N/A INVALID (Not Allowed) Data 0 0 1
Write to Buffer (Note 5)
Notes:
1. 2. 3. 4. 5. DQ5 switches to 1 when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. DQ7 a valid address when reading status information. Refer to the appropriate subsection for further details. Data are invalid for addresses in a Program Suspended sector. DQ1 indicates the Write to Buffer ABORT status during Write Buffer Programming operations. The data-bar polling algorithm should be used for Write Buffer Programming operations. Note that DQ7# during Write Buffer Programming indicates the data-bar for DQ7 data for the Last Loaded Write-buffer Address location.
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8.6
Simultaneous Read/Write
The simultaneous read/write feature allows the host system to read data from one bank of memory while programming or erasing another bank of memory. An erase operation may also be suspended to read from or program another location within the same bank (except the sector being erased). Figure 12.24, Back-to-Back Read/Write Cycle Timings, shows how read and write cycles may be initiated for simultaneous operation with zero latency. Refer to the DC Characteristics table for read-while-program and read-while-erase current specification.
8.7
Writing Commands/Command Sequences
When the device is configured for Asynchronous read, only Asynchronous write operations are allowed, and CLK is ignored. When in the Synchronous read mode configuration, the device is able to perform both Asynchronous and Synchronous write operations. CLK and AVD# induced address latches are supported in the Synchronous programming mode. During a synchronous write operation, to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive AVD# and CE# to VIL, and OE# to VIH when providing an address to the device, and drive WE# and CE# to VIL, and OE# to VIH when writing commands or data. During an asynchronous write operation, the system must drive CE# and WE# to VIL and OE# to VIH when providing an address, command, and data. Addresses are latched on the last falling edge of WE# or CE#, while data is latched on the 1st rising edge of WE# or CE#. An erase operation can erase one sector, multiple sectors, or the entire device. Tables 7.1-7.3 indicate the address space that each sector occupies. The device address space is divided into sixteen banks: Banks 1 through 14 contain only 64 Kword sectors, while Banks 0 and 15 contain both 16 Kword boot sectors in addition to 64 Kword sectors. A bank address is the set of address bits required to uniquely select a bank. Similarly, a sector address is the address bits required to uniquely select a sector. ICC2 in DC Characteristics represents the active current specification for the write mode. AC Characteristics--Synchronous and AC Characteristics-- Asynchronous Read contain timing specification tables and timing diagrams for write operations.
8.8
Handshaking
The handshaking feature allows the host system to detect when data is ready to be read by simply monitoring the RDY (Ready) pin, which is a dedicated output and controlled by CE#. When the device is configured to operate in synchronous mode, and OE# is low (active), the initial word of burst data becomes available after either the falling or rising edge of the RDY pin (depending on the setting for bit 10 in the Configuration Register). It is recommended that the host system set CR13-CR11 in the Configuration Register to the appropriate number of wait states to ensure optimal burst mode operation (see Table 8.8, Configuration Register). Bit 8 in the Configuration Register allows the host to specify whether RDY is active at the same time that data is ready, or one cycle before data is ready.
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8.9
Hardware Reset
The RESET# input provides a hardware method of resetting the device to reading array data. When RESET# is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/ write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. To ensure data integrity the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence. When RESET# is held at VSS, the device draws CMOS standby current (ICC4). If RESET# is held at VIL, but not at VSS, the standby current is greater. RESET# may be tied to the system reset circuitry which enables the system to read the boot-up firmware from the Flash memory upon a system reset. See Figures 12.5 and 12.12 for timing diagrams.
8.10
Software Reset
Software reset is part of the command set (see Table 13.1) that also returns the device to array read mode and must be used for the following conditions: 1. 2. 3. 4. 5. to exit Autoselect mode when DQ5 goes high during write status operation that indicates program or erase cycle was not successfully completed exit sector lock/unlock operation. to return to erase-suspend-read mode if the device was previously in Erase Suspend mode. after any aborted operations
Software Functions and Sample Code
Table 8.24
Cycle Reset Command Operation Write
Reset
Byte Address Base + xxxh Word Address Base + xxxh Data 00F0h
(LLD Function = lld_ResetCmd)
Note: Base = Base Address.
The following is a C source code example of using the reset function. Refer to the Spansion Low Level Driver User's Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Reset (software reset of Flash state machine) */ *( (UINT16 *)base_addr + 0x000 ) = 0x00F0;
The following are additional points to consider when using the reset command: This command resets the banks to the read and address bits are ignored. Reset commands are ignored once erasure has begun until the operation is complete. Once programming begins, the device ignores reset commands until the operation is complete The reset command may be written between the cycles in a program command sequence before programming begins (prior to the third cycle). This resets the bank to which the system was writing to the read mode.
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If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. The reset command may be also written during an Autoselect command sequence. If a bank has entered the Autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ1 goes high during a Write Buffer Programming operation, the system must write the Write to Buffer Abort Reset command sequence to RESET the device to reading array data. The standard RESET command does not work during this condition. To exit the unlock bypass mode, the system must issue a two-cycle unlock bypass reset command sequence [see command table for details].
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9
Advanced Sector Protection/Unprotection
The Advanced Sector Protection/Unprotection feature disables or enables programming or erase operations in any or all sectors and can be implemented through software and/or hardware methods, which are independent of each other. This section describes the various methods of protecting data stored in the memory array. An overview of these methods in shown in Figure 9.1.
Hardware Methods
Software Methods
Lock Register
(One Time Programmable)
ACC = VIL (All sectors locked)
Password Method
(DQ2)
Persistent Method
(DQ1)
(All boot sectors locked)
WP# = VIL
64-bit Password
(One Time Protect)
PPB Lock Bit1,2,3 0 = PPBs Locked 1 = PPBs Unlocked
1. Bit is volatile, and defaults to "1" on reset. 2. Programming to "0" locks all PPBs to their current state. 3. Once programmed to "0", requires hardware reset to unlock.
Memory Array
Sector 0 Sector 1 Sector 2
Persistent Protection Bit (PPB)4,5
PPB 0 PPB 1 PPB 2
Dynamic Protection Bit (PPB)6,7,8
DYB 0 DYB 1 DYB 2
Sector N-2 Sector N-1 Sector N
3
PPB N-2 PPB N-1 PPB N
4. 0 = Sector Protected, 1 = Sector Unprotected. 5. PPBs programmed individually, but cleared collectively
DYB N-2 DYB N-1 DYB N
6. 0 = Sector Protected, 1 = Sector Unprotected. 7. Protect effective only if PPB Lock Bit is unlocked and corresponding PPB is "1" (unprotected). 8. Volatile Bits: defaults to user choice upon power-up (see ordering options).
3. N = Highest Address Sector.
Figure 9.1
Advanced Sector Protection/Unprotection
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9.1
Lock Register
As shipped from the factory, all devices default to the persistent mode when power is applied, and all sectors are unprotected, unless otherwise chosen through the DYB ordering option. The device programmer or host system must then choose which sector protection method to use. Programming (setting to 0) any one of the following two one-time programmable, non-volatile bits locks the part permanently in that mode: Lock Register Persistent Protection Mode Lock Bit (DQ1) Lock Register Password Protection Mode Lock Bit (DQ2)
Table 9.1
Device
S29WS256N
Lock Register
DQ3
1
DQ15-05
1
DQ4
1
DQ2
Password Protection Mode Lock Bit
DQ1
Persistent Protection Mode Lock Bit
DQ0
Customer Secured Silicon Sector Protection Bit
DYB Lock Boot Bit S29WS128N/ S29WS064N 0 = sectors power up protected 1 = sectors power up unprotected
PPB One-Time Programmable Bit 0 = All PPB erase command disabled 1 = All PPB Erase command enabled
Undefined
Password Protection Mode Lock Bit
Persistent Protection Mode Lock Bit
Secured Silicon Sector Protection Bit
For programming lock register bits refer to Table 13.2. Notes 1. If the password mode is chosen, the password must be programmed before setting the corresponding lock register bit. 2. After the Lock Register Bits Command Set Entry command sequence is written, reads and writes for Bank 0 are disabled, while reads from other banks are allowed until exiting this mode. 3. If both lock bits are selected to be programmed (to zeros) at the same time, the operation aborts. 4. Once the Password Mode Lock Bit is programmed, the Persistent Mode Lock Bit is permanently disabled, and no changes to the protection scheme are allowed. Similarly, if the Persistent Mode Lock Bit is programmed, the Password Mode is permanently disabled. After selecting a sector protection method, each sector can operate in any of the following three states: 1. 2. 3. Constantly locked. The selected sectors are protected and can not be reprogrammed unless PPB lock bit is cleared via a password, hardware reset, or power cycle. Dynamically locked. The selected sectors are protected and can be altered via software commands. Unlocked. The sectors are unprotected and can be erased and/or programmed.
These states are controlled by the bit types described in Sections 9.2-9.6.
9.2
Persistent Protection Bits
The Persistent Protection Bits are unique and nonvolatile for each sector and have the same endurances as the Flash memory. Preprogramming and verification prior to erasure are handled by the device, and therefore do not require system monitoring.
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Notes 1. 2. 3. 4. 5. 6. 7. 8. 9. Each PPB is individually programmed and all are erased in parallel. While programming PPB for a sector, array data can be read from any other bank, except Bank 0 (used for Data# Polling) and the bank in which sector PPB is being programmed. Entry command disables reads and writes for the bank selected. Reads within that bank return the PPB status for that sector. Reads from other banks are allowed while writes are not allowed. All Reads must be performed using the Asynchronous mode. The specific sector address (A23-A14 WS256N, A22-A14 WS128N, A21-A14 WS064N) are written at the same time as the program command. If the PPB Lock Bit is set, the PPB Program or erase command does not execute and timesout without programming or erasing the PPB. There are no means for individually erasing a specific PPB and no specific sector address is required for this operation.
10. Exit command must be issued after the execution which resets the device to read mode and re-enables reads and writes for Bank 0 11. The programming state of the PPB for a given sector can be verified by writing a PPB Status Read Command to the device as described by the flow chart shown in Figure 9.2.
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Enter PPB Command Set. Addr = BA
Program PPB Bit. Addr = SA
Read Byte Twice Addr = SA0
DQ6 = Toggle? Yes No
No
DQ5 = 1? Yes Read Byte Twice Addr = SA0 Wait 500 s
DQ6 = Toggle? Yes
No
Read Byte. Addr = SA
No
DQ0 = '1' (Erase) '0' (Pgm.)? Yes
FAIL
Issue Reset Command
PASS
Exit PPB Command Set
Figure 9.2
PPB Program/Erase Algorithm
9.3
Dynamic Protection Bits
Dynamic Protection Bits are volatile and unique for each sector and can be individually modified. DYBs only control the protection scheme for unprotected sectors that have their PPBs cleared (erased to 1). By issuing the DYB Set or Clear command sequences, the DYBs are set (programmed to 0) or cleared (erased to 1), thus placing each sector in the protected or unprotected state respectively. This feature allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed.
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Notes 1. The DYBs can be set (programmed to 0) or cleared (erased to 1) as often as needed. When the parts are first shipped, the PPBs are cleared (erased to 1) and upon power up or reset, the DYBs can be set or cleared depending upon the ordering option chosen. 2. 3. 4. 5. If the option to clear the DYBs after power up is chosen, (erased to 1), then the sectorsmay be modified depending upon the PPB state of that sector (see Table 9.2). The sectors would be in the protected state If the option to set the DYBs after power up is chosen (programmed to 0). It is possible to have sectors that are persistently locked with sectors that are left in the dynamic state. The DYB Set or Clear commands for the dynamic sectors signify protected or unprotected state of the sectors respectively. However, if there is a need to change the status of the persistently locked sectors, a few more steps are required. First, the PPB Lock Bit must be cleared by either putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB Lock Bit once again locks the PPBs, and the device operates normally again. To achieve the best protection, it is recommended to execute the PPB Lock Bit Set command early in the boot code and protect the boot code by holding WP# = VIL. Note that the PPB and DYB bits have the same function when ACC = VHH as they do when ACC =VIH.
6.
9.4
Persistent Protection Bit Lock Bit
The Persistent Protection Bit Lock Bit is a global volatile bit for all sectors. When set (programmed to 0), it locks all PPBs and when cleared (programmed to 1), allows the PPBs to be changed. There is only one PPB Lock Bit per device. Notes 1. 2. No software command sequence unlocks this bit unless the device is in the password protection mode; only a hardware reset or a power-up clears this bit. The PPB Lock Bit must be set (programmed to 0) only after all PPBs are configured to the desired settings.
9.5
Password Protection Method
The Password Protection Method allows an even higher level of security than the Persistent Sector Protection Mode by requiring a 64 bit password for unlocking the device PPB Lock Bit. In addition to this password requirement, after power up and reset, the PPB Lock Bit is set 0 to maintain the password mode of operation. Successful execution of the Password Unlock command by entering the entire password clears the PPB Lock Bit, allowing for sector PPBs modifications.
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Notes 1. There is no special addressing order required for programming the password. Once the Password is written and verified, the Password Mode Locking Bit must be set in order to prevent access. The Password Program Command is only capable of programming 0s. Programming a 1 after a cell is programmed as a 0 results in a time-out with the cell as a 0. The password is all 1s when shipped from the factory. All 64-bit password combinations are valid as a password. There is no means to verify what the password is after it is set. The Password Mode Lock Bit, once set, prevents reading the 64-bit password on the data bus and further password programming. The Password Mode Lock Bit is not erasable. The lower two address bits (A1-A0) are valid during the Password Read, Password Program, and Password Unlock. The exact password must be entered in order for the unlocking function to occur.
2. 3. 4. 5. 6. 7. 8. 9.
10. The Password Unlock command cannot be issued any faster than 1 s at a time to prevent a hacker from running through all the 64-bit combinations in an attempt to correctly match a password. 11. Approximately 1 s is required for unlocking the device after the valid 64-bit password is given to the device. 12. Password verification is only allowed during the password programming operation. 13. All further commands to the password region are disabled and all operations are ignored. 14. If the password is lost after setting the Password Mode Lock Bit, there is no way to clear the PPB Lock Bit. 15. Entry command sequence must be issued prior to any of any operation and it disables reads and writes for Bank 0. Reads and writes for other banks excluding Bank 0 are allowed. 16. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. 17. A program or erase command to a protected sector enables status polling and returns to read mode without having modified the contents of the protected sector. 18. The programming of the DYB, PPB, and PPB Lock for a given sector can be verified by writing individual status read commands DYB Status, PPB Status, and PPB Lock Status to the device.
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Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h
Unlock Cycle 1 Unlock Cycle 2
Write Enter Lock Register Command: Address 555h, Data 40h
Program Lock Register Data Address XXXh, Data A0h Address 77h*, Data PD
XXXh = Address don't care * Not on future devices Program Data (PD): See text for Lock Register definitions Caution: Lock register can only be progammed once.
Wait 4 s
Perform Polling Algorithm
(see Write Operation Status flowchart)
Yes
Done?
No DQ5 = 1? Yes No Error condition (Exceeded Timing Limits)
PASS. Write Lock Register Exit Command: Address XXXh, Data 90h Address XXXh, Data 00h Device returns to reading array.
FAIL. Write rest command to return to reading array.
Figure 9.3
Lock Register Program Algorithm
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9.6
Advanced Sector Protection Software Examples
Table 9.2
Unique Device PPB Lock Bit 0 = locked 1 = unlocked
Any Sector Any Sector Any Sector Any Sector Any Sector Any Sector Any Sector Any Sector 0 0 0 0 1 1 1 1
Sector PPB 0 = protected 1 = unprotected
0 0 1 1 0 0 1 1
Sector DYB 0 = protected 1 = unprotected
x x 1 0 x x 0 1
Sector Protection Status
Protected through PPB Protected through PPB Unprotected Protected through DYB Protected through PPB Protected through PPB Protected through DYB Unprotected
Table 9.2 contains all possible combinations of the DYB, PPB, and PPB Lock Bit relating to the status of the sector. In summary, if the PPB Lock Bit is locked (set to 0), no changes to the PPBs are allowed. The PPB Lock Bit can only be unlocked (reset to 1) through a hardware reset or power cycle. See also Figure 9.1 for an overview of the Advanced Sector Protection feature.
9.7
Hardware Data Protection Methods
The device offers two main types of data protection at the sector level via hardware control: When WP# is at VIL, the four outermost sectors are locked (device specific). When ACC is at VIL, all sectors are locked. There are additional methods by which intended or accidental erasure of any sectors can be prevented via hardware means. The following subsections describes these methods:
9.7.1
WP# Method
The Write Protect feature provides a hardware method of protecting the four outermost sectors. This function is provided by the WP# pin and overrides the previously discussed Sector Protection/Unprotection method. If the system asserts VIL on the WP# pin, the device disables program and erase functions in the outermost boot sectors. The outermost boot sectors are the sectors containing both the lower and upper set of sectors in a dual-boot-configured device. If the system asserts VIH on the WP# pin, the device reverts to whether the boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected. Note that the WP# pin must not be left floating or unconnected as inconsistent behavior of the device may result. The WP# pin must be held stable during a command sequence execution
9.7.2
ACC Method
This method is similar to above, except it protects all sectors. Once ACC input is set to VIL, all program and erase functions are disabled and hence all sectors are protected.
9.7.3
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down.
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The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control inputs to prevent unintentional writes when VCC is greater than VLKO.
9.7.4 9.7.5
Write Pulse Glitch Protection
Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Power-Up Write Inhibit
If WE# = CE# = RESET# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up.
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10 Power Conservation Modes
10.1 Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# inputs are both held at VCC 0.2 V. The device requires standard access time (tCE) for read access, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 in DC Characteristics represents the standby current specification
10.2
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption while in asynchronous mode. the device automatically enables this mode when addresses remain stable for tACC + 20 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. While in synchronous mode, the automatic sleep mode is disabled. Note that a new burst operation is required to provide new data. ICC6 in DC Characteristics represents the automatic sleep mode current specification.
10.3
Hardware RESET# Input Operation
The RESET# input provides a hardware method of resetting the device to reading array data. When RESET# is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/ write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence to ensure data integrity. When RESET# is held at VSS 0.2 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS 0.2 V, the standby current is greater. RESET# may be tied to the system reset circuitry and thus, a system reset would also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.
10.4
Output Disable (OE#)
When the OE# input is at VIH, output from the device is disabled. The outputs are placed in the high impedance state.
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11
Secured Silicon Sector Flash Memory Region
The Secured Silicon Sector provides an extra Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The Secured Silicon Sector is 256 words in length that consists of 128 words for factory data and 128 words for customer-secured areas. All Secured Silicon reads outside of the 256-word address range returns invalid data. The Factory Indicator Bit, DQ7, (at Autoselect address 03h) is used to indicate whether or not the Factory Secured Silicon Sector is locked when shipped from the factory. The Customer Indicator Bit (DQ6) is used to indicate whether or not the Customer Secured Silicon Sector is locked when shipped from the factory. Please note the following general conditions: While Secured Silicon Sector access is enabled, simultaneous operations are allowed except for Bank 0. On power-up, or following a hardware reset, the device reverts to sending commands to the normal address space. Reads can be performed in the Asynchronous or Synchronous mode. Burst mode reads within Secured Silicon Sector wrap from address FFh back to address 00h. Reads outside of sector 0 return memory array data. Continuous burst read past the maximum address is undefined. Sector 0 is remapped from memory array to Secured Silicon Sector array. Once the Secured Silicon Sector Entry Command is issued, the Secured Silicon Sector Exit command must be issued to exit Secured Silicon Sector Mode. The Secured Silicon Sector is not accessible when the device is executing an Embedded Program or Embedded Erase algorithm.
Table 11.1
Sector Customer Factory Sector Size 128 words 128 words
Addresses
Address Range 000080h-0000FFh 000000h-00007Fh
11.1
Factory Secured SiliconSector
The Factory Secured Silicon Sector is always protected when shipped from the factory and has the Factory Indicator Bit (DQ7) permanently set to a 1. This prevents cloning of a factory locked part and ensures the security of the ESN and customer code once the product is shipped to the field. These devices are available pre programmed with one of the following: A random, 8 Word secure ESN only within the Factory Secured Silicon Sector Customer code within the Customer Secured Silicon Sector through the SpansionTM programming service. Both a random, secure ESN and customer code through the Spansion programming service. Customers may opt to have their code programmed through the Spansion programming services. Spansion programs the customer's code, with or without the random ESN. The devices are then shipped from the Spansion factory with the Factory Secured Silicon Sector and Customer Secured Silicon Sector permanently locked. Contact your local representative for details on using Spansion programming services.
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11.2
Customer Secured Silicon Sector
The Customer Secured Silicon Sector is typically shipped unprotected (DQ6 set to 0), allowing customers to utilize that sector in any manner they choose. If the security feature is not required, the Customer Secured Silicon Sector can be treated as an additional Flash memory space. Please note the following: Once the Customer Secured Silicon Sector area is protected, the Customer Indicator Bit is permanently set to 1. The Customer Secured Silicon Sector can be read any number of times, but can be programmed and locked only once. The Customer Secured Silicon Sector lock must be used with caution as once locked, there is no procedure available for unlocking the Customer Secured Silicon Sector area and none of the bits in the Customer Secured Silicon Sector memory space can be modified in any way. The accelerated programming (ACC) and unlock bypass functions are not available when programming the Customer Secured Silicon Sector, but reading in Banks 1 through 15 is available. Once the Customer Secured Silicon Sector is locked and verified, the system must write the Exit Secured Silicon Sector Region command sequence which return the device to the memory array at sector 0.
11.3
Secured Silicon Sector Entry and Secured Silicon Sector Exit Command Sequences
The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon Sector command sequence. The device continues to access the Secured Silicon Sector region until the system issues the four-cycle Exit Secured Silicon Sector command sequence. See Command Definition Table [Secured Silicon Sector Command Table, Appendix Table 13.1 for address and data requirements for both command sequences. The Secured Silicon Sector Entry Command allows the following commands to be executed Read customer and factory Secured Silicon areas Program the customer Secured Silicon Sector After the system has written the Enter Secured Silicon Sector command sequence, it may read the Secured Silicon Sector by using the addresses normally occupied by sector SA0 within the memory array. This mode of operation continues until the system issues the Exit Secured Silicon Sector command sequence, or until power is removed from the device.
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Software Functions and Sample Code
The following are C functions and source code examples of using the Secured Silicon Sector Entry, Program, and exit commands. Refer to the Spansion Low Level Driver User's Guide (available soon on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines.
Table 11.2
Cycle Unlock Cycle 1 Unlock Cycle 2 Entry Cycle
Secured Silicon Sector Entry
Byte Address Base + AAAh Base + 554h Base + AAAh Word Address Base + 555h Base + 2AAh Base + 555h Data 00AAh 0055h 0088h
(LLD Function = lld_SecSiSectorEntryCmd)
Operation Write Write Write
Note: Base = Base Address.
/* Example: SecSi Sector *( (UINT16 *)base_addr *( (UINT16 *)base_addr *( (UINT16 *)base_addr
Entry Command */ + 0x555 ) = 0x00AA; + 0x2AA ) = 0x0055; + 0x555 ) = 0x0088;
/* write unlock cycle 1 /* write unlock cycle 2 /* write Secsi Sector Entry Cmd
*/ */ */
Table 11.3
Cycle Unlock Cycle 1 Unlock Cycle 2 Program Setup Program
Secured Silicon Sector Program
Byte Address Base + AAAh Base + 554h Base + AAAh Word Address Word Address Base + 555h Base + 2AAh Base + 555h Word Address Data 00AAh 0055h 00A0h Data Word
(LLD Function = lld_ProgramCmd)
Operation Write Write Write Write
Note: Base = Base Address.
/* Once in the SecSi Sector mode, you program */ /* words using the programming algorithm. */
Table 11.4
Cycle Unlock Cycle 1 Unlock Cycle 2 Exit Cycle
Secured Silicon Sector Exit
Byte Address Base + AAAh Base + 554h Base + AAAh Word Address Base + 555h Base + 2AAh Base + 555h Data 00AAh 0055h 0090h
(LLD Function = lld_SecSiSectorExitCmd)
Operation Write Write Write
Note: Base = Base Address.
/* Example: SecSi Sector *( (UINT16 *)base_addr *( (UINT16 *)base_addr *( (UINT16 *)base_addr *( (UINT16 *)base_addr Exit Command */ + 0x555 ) = 0x00AA; + 0x2AA ) = 0x0055; + 0x555 ) = 0x0090; + 0x000 ) = 0x0000; /* /* /* /* write write write write unlock cycle unlock cycle SecSi Sector SecSi Sector 1 2 Exit cycle 3 Exit cycle 4 */ */ */ */
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12 Electrical Specifications
12.1 Absolute Maximum Ratings
Storage Temperature Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +125C Voltage with Respect to Ground: All Inputs and I/Os except as noted below (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VIO + 0.5 V VCC (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 V to +2.5 V VIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 V to +2.5 V ACC (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 V to +9.5 V Output Short Circuit Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Notes:
1. Minimum DC voltage on input or I/Os is -0.5 V. During voltage transitions, inputs or I/Os may undershoot VSS to -2.0 V for periods of up to 20 ns. See Figure 12.1. Maximum DC voltage on input or I/Os is VCC + 0.5 V. During voltage transitions outputs may overshoot to VCC + 2.0 V for periods up to 20 ns. See Figure 12.2. Minimum DC input voltage on pin ACC is -0.5V. During voltage transitions, ACC may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 12.1. Maximum DC voltage on pin ACC is +9.5 V, which may overshoot to 10.5 V for periods up to 20 ns. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
2.
3. 4.
20 ns +0.8 V -0.5 V -2.0 V 20 ns
20 ns
VCC +2.0 V VCC +0.5 V 1.0 V 20 ns
20 ns
20 ns
Figure 12.1 Maximum Negative Overshoot Waveform
Preliminary for the S29W256N.
Figure 12.2 Maximum Positive Overshoot Waveform
Note: The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document is
12.2
Operating Ranges
Wireless (W) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25C to +85C
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C
Supply Voltages
VCC Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+1.70 V to +1.95 V VIO Supply Voltages: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.70 V to +1.95 V (Contact local sales office for VIO = 1.35 to +1.70 V.)
Note: Operating ranges define those limits between which the device functionality is guaranteed.
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12.3
Test Conditions
Device Under Test CL
Figure 12.3 Table 12.1
Test Condition Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels
Test Setup
Test Specifications
All Speed Options 30 3.0 @ 54, 66 MHz 2.5 @ 80 MHz 0.0-VIO VIO/2 VIO/2 Unit pF ns V V V
Note: The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document
is Preliminary for the S29W256N.
12.4
Key to Switching Waveforms
Waveform Inputs Steady Changing from H to L Changing from L to H Don't Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) Outputs
Note: The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document
is Preliminary for the S29W256N.
12.5
Switching Waveforms
All Inputs and Outputs VIO 0.0 V Input VIO/2 Measurement Level VIO/2 Output
Figure 12.4
Input Waveforms and Measurement Levels
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12.6
VCC Power-up
Parameter tVCS
Notes:
1. 2. 3. VCC >= VIO - 100mV and VCC ramp rate is > 1V / 100s VCC ramp rate <1V / 100s, a Hardware Reset is required. The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document is Preliminary for the S29W256N.
Description VCC Setup Time
Test Setup Min
Speed 1
Unit ms
tVCS VCC
VIO
RESET#
Figure 12.5
VCC Power-up Diagram
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12.7
DC Characteristics
(CMOS Compatible)
Parameter ILI ILO Description (Notes) Input Load Current Output Leakage Current (3) Test Conditions (Notes 1, 2, 9) VIN = VSS to VCC, VCC = VCCmax VOUT = VSS to VCC, VCC = VCCmax 54 MHz CE# = VIL, OE# = VIH, WE# = VIH, burst length = 8 66 MHz 80 MHz 54 MHz CE# = VIL, OE# = VIH, WE# = VIH, burst length = 16 ICCB VCC Active burst Read Current CE# = VIL, OE# = VIH, WE# = VIH, burst length = 32 CE# = VIL, OE# = VIH, WE# = VIH, burst length = Continuous IIO1 ICC1 VIO Non-active Output VCC Active Asynchronous Read Current (4) OE# = VIH 10 MHz CE# = VIL, OE# = VIH, WE# = VIH CE# = VIL, OE# = VIH, ACC = VIH CE# = RESET# = VCC 0.2 V RESET# = VIL, CLK = VIL CE# = VIL, OE# = VIH, ACC = VIH @ 5 MHz CE# = VIL, OE# = VIH CE# = VIL, OE# = VIH, VACC = 9.5 V VIO = 1.8 V VIO = 1.8 V IOL = 100 A, VCC = VCC min = VIO IOH = -100 A, VCC = VCC min = VIO VIO - 0.1 8.5 1.0 9.5 1.4 VACC VCC -0.5 VIO - 0.4 5 MHz 1 MHz VACC VCC VACC VCC 66 MHz 80 MHz 54 MHz 66 MHz 80 MHz 54 MHz 66 MHz 80 MHz 27 28 30 28 30 32 29 32 34 32 35 38 20 27 13 3 1 19 1 20 70 50 2 6 14 Min Typ Max 1 1 54 60 66 48 54 60 42 48 54 36 42 48 30 36 18 4 5 52.5 5 40 150 60 40 20 20 0.4 VIO + 0.4 0.1 Unit A A mA mA mA mA mA mA mA mA mA mA mA mA A mA mA mA A mA A A A mA A mA mA V V V V V V
ICC2 ICC3 ICC4 ICC5 ICC6 IACC VIL VIH VOL VOH VHH VLKO
VCC Active Write Current (5) VCC Standby Current (6, 7) VCC Reset Current (7) VCC Active Current (Read While Write) (7) VCC Sleep Current (7) Accelerated Program Current (8) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Voltage for Accelerated Program Low VCC Lock-out Voltage
Notes:
Maximum ICC specifications are tested with VCC = VCCmax. VCC= VIO. CE# must be set high when measuring the RDY pin. The ICC current listed is typically less than 3 mA/MHz, with OE# at VIH. ICC active while Embedded Erase or Embedded Program is in progress. Device enters automatic sleep mode when addresses are stable for tACC + 20 ns. Typical sleep mode current is equal to ICC3. 7. VIH = VCC 0.2 V and VIL > -0.1 V. 8. Total current during accelerated programming is the sum of VACC and VCC currents. 9. VACC = VHH on ACC input. 10. The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document is Preliminary for the S29W256N. 1. 2. 3. 4. 5. 6.
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12.8
AC Characteristics
CLK Characterization
Parameter fCLK tCLK tCH tCL tCR tCF Description CLK Frequency CLK Period CLK High Time CLK Low Time CLK Rise Time CLK Fall Time Max Min Min 54 MHz 54 18.5 7.4 66 MHz 66 15.1 6.1 80 MHz 80 12.5 5.0 Unit MHz ns ns
12.8.1
Max
3
3
2.5
ns
Note: The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document
is Preliminary for the S29W256N.
tCLK tCH tCL
CLK
tCR
tCF
Figure 12.6 12.8.2 Synchronous/Burst Read
Parameter JEDEC Standard tIACC tBACC tACS tACH tBDH tCR tOE tCEZ tOEZ tCES tRDYS tRACC tCAS tAVC tAVD tAOE
Notes:
1. 2. 3.
CLK Characterization
Description Latency Burst Access Time Valid Clock to Output Delay Address Setup Time to CLK (Note 1) Address Hold Time from CLK (Note 1) Data Hold Time from Next Clock Cycle Chip Enable to RDY Valid Output Enable to Output Valid Chip Enable to High Z (Note 2) Output Enable to High Z (Note 2) CE# Setup Time to CLK RDY Setup Time to CLK Ready Access Time from CLK CE# Setup Time to AVD# AVD# Low to CLK AVD# Pulse AVD Low to OE# Low Max Max Min Min Min Max Max Max Max Min Min Max Min Min Min Max
54 MHz 13.5 5 7 4 13.5 13.5
66 MHz 80 11.2 4 6 3 11.2
80 MHz 9
Unit ns ns ns ns ns
9 11.2
ns ns ns ns ns
10 10 4 5 13.5 4 11.2 0 4 8 38.4 3.5 9
ns ns ns ns ns ns
Addresses are latched on the first rising edge of CLK. Not 100% tested. The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document is Preliminary for the S29W256N.
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12.8.3
Timing Diagrams
5 cycles for initial access shown.
tCES CE# 1 CLK tAVC AVD# tACS Addresses
Aa
18.5 ns typ. (54 MHz)
tCEZ 6 7
2
3
4
5
tAVD
tACH Data (n) tIACC tAOE OE# tOE RDY (n)
Hi-Z Da Da + 1
tBACC
Hi-Z Da + 2 Da + 3 Da + n
tBDH tRACC
tOEZ
Hi-Z
tCR
tRDYS
Hi-Z Da Da + 1 Da + 2 Da + 2 Da + n
Data (n + 1)
RDY (n + 1)
Hi-Z
Hi-Z
Data (n + 2)
Da Da + 1 Da + 1 Da + 1 Da + n
Hi-Z
RDY (n + 2)
Hi-Z
Hi-Z
Data (n + 3)
Da Da Da Da Da + n
Hi-Z
RDY (n + 3)
Hi-Z
Hi-Z
Notes:
1. 2. 3. Figure shows total number of wait states set to five cycles. The total number of wait states can be programmed from two cycles to seven cycles. If any burst address occurs at address + 1 , address + 2, or address + 3, additional clock delay cycles are inserted, and are indicated by RDY. The device is in synchronous mode.
Figure 12.7
CLK Synchronous Burst Mode Read
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tCES CE# 1 CLK tAVC AVD# tACS Addresses
Ac
7 cycles for initial access shown.
2
3
4
5
6
7
tAVD
tACH Data tIACC tAOE OE# tCR RDY
Hi-Z DC DD
tBACC
DE
DF
D8
DB
tBDH tRACC
tOE
tRACC
tRDYS
Notes:
1. 2. 3. 4. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven cycles. If any burst address occurs at address + 1 , address + 2, or address + 3, additional clock delay cycles are inserted, and are indicated by RDY. The device is in synchronous mode with wrap around. D8-DF in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting address in figure is the 4th address in range (0-F).
Figure 12.8
tCES CE# 1 CLK tAVC AVD# tACS Addresses
Ac
8-word Linear Burst with Wrap Around
7 cycles for initial access shown.
2
3
4
5
6
7
tAVD
tACH Data tAOE OE# tCR RDY
Hi-Z
tBACC tIACC
DC
DD
DE
DF
D10
D13
tBDH
tOE
tRACC
tRACC
tRDYS
Notes:
1. 2. 3. 4. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven cycles. Clock is set for active rising edge. If any burst address occurs at address + 1 , address + 2, or address + 3, additional clock delay cycles are inserted, and are indicated by RDY. The device is in asynchronous mode with out wrap around. DC-D13 in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting address in figure is the 1st address in range (c-13).
Figure 12.9 8-word Linear Burst without Wrap Around
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tCES CE# 1 CLK tAVC AVD# tACS Addresses
Aa
6 wait cycles for initial access shown.
tCEZ 6
2
3
4
5
tAVD
tACH Data tIACC tAOE OE# tCR RDY
Hi-Z Da Da+1
tBACC
Hi-Z Da+2 Da+3 Da + n
tBDH tRACC tOE
tOEZ
Hi-Z
tRDYS
Notes:
1. 2. Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence has been written with CR8=0; device outputs RDY one cycle before valid data.
Figure 12.10 12.8.4
Linear Burst with RDY Set One Cycle Before Data
AC Characteristics--Asynchronous Read
Parameter JEDEC Standard Description 54 MHz 66 MHz 80 MHz Unit
tCE tACC tAVDP tAAVDS tAAVDH tOE tOEH tOEZ tCAS
Notes:
1. 2.
Access Time from CE# Low Asynchronous Access Time AVD# Low Time Address Setup Time to Rising Edge of AVD# Address Hold Time from Rising Edge of AVD# Output Enable to Output Valid Output Enable Hold Time Read Data# Polling
Max Max Min Min Min Max Min Min Max Min 7
80 80 8 4 6 13.5 0 10 10 0
ns ns ns ns ns ns ns ns ns ns
Output Enable to High Z (see Note) CE# Setup Time to AVD#
Not 100% tested. The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document is Preliminary for the S29W256N.
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CE# tOE tOEH WE# Data tACC Addresses tCAS AVD# tAVDP tAAVDS
Note: RA = Read Address, RD = Read Data.
OE#
tCE Valid RD
tOEZ
RA tAAVDH
Figure 12.11 Asynchronous Mode Read 12.8.5 Hardware Reset (RESET#)
Parameter JEDEC Std. tRP tRH
Notes:
1. 2. Not 100% tested. The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document is Preliminary for the S29W256N.
Description RESET# Pulse Width Reset High Time Before Read (See Note) Min Min
All Speed Options 30 200
Unit s ns
CE#, OE# tRH RESET# tRP
Figure 12.12
Reset Timings
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12.8.6
Erase/Program Timing
Parameter JEDEC tAVAV tAVWL tWLAX Standard tWC tAS tAH tAVDP tDVWH tWHDX tGHWL tWHEH tWLWH tWHWL tDS tDH tGHWL tCAS tCH tWP tWPH tSR/W tVID tVIDS tVCS tELWL tCS tAVSW tAVHW tAVSC tAVHC tCSW tWEP tSEA tESL tPSL tASP tPSP Description Write Cycle Time (Note 1) Address Setup Time (Notes 2, 3) Address Hold Time (Notes 2, 3) AVD# Low Time Data Setup Time Data Hold Time Read Recovery Time Before Write CE# Setup Time to AVD# CE# Hold Time Write Pulse Width Write Pulse Width High Latency Between Read and Write Operations VACC Rise and Fall Time VACC Setup Time (During Accelerated Programming) VCC Setup Time CE# Setup Time to WE# AVD# Setup Time to WE# AVD# Hold Time to WE# AVD# Setup Time to CLK AVD# Hold Time to CLK Clock Setup Time to WE# Noise Pulse Margin on WE# Sector Erase Accept Time-out Erase Suspend Latency Program Suspend Latency Toggle Time During Sector Protection Toggle Time During Programming Within a Protected Sector Synchronous Asynchronous Synchronous Asynchronous Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Max Max Max Max Typ Typ 45 0 0 0 0 30 20 0 500 1 50 5 5 5 5 5 5 3 50 20 20 100 1 54 MHz 66 MHz 80 5 0 9 20 8 20 80 MHz Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s ns ns ns ns ns ns ns s s s s s
Notes:
1. 2. 3. 4. 5. 6. Not 100% tested. Asynchronous read mode allows Asynchronous program operation only. Synchronous read mode allows both Asynchronous and Synchronous program operation. In asynchronous program operation timing, addresses are latched on the falling edge of WE#. In synchronous program operation timing, addresses are latched on the rising edge of CLK. See the Erase and Programming Performance section for more information. Does not include the preprogramming time. The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document is Preliminary for the S29W256N.
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VIH
Erase Command Sequence (last two cycles)
Read Status Data
CLK
VIL
tAVDP AVD# tAS Addresses 2AAh tAH SA
555h for chip erase 10h for chip erase
VA
In Progress
VA
Data
55h
30h tDS tDH
Complete
CE#
OE# tWP WE# tCS tVCS VCC
tCH
tWHWH2 tWPH tWC
Figure 12.13
Chip/Sector Erase Operation Timings
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Program Command Sequence (last two cycles)
Read Status Data
VIH
CLK
VIL
tAVSW tAVDP tAVHW
AVD tAS tAH Addresses 555h PA VA
In Progress
VA
Data tCAS CE#
A0h tDS tDH
PD
Complete
OE# tWP WE#
tCH
tWHWH1 tCS tWC tVCS VCC tWPH
Notes:
1. 2. 3. 4. 5. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. In progress and complete refer to status of program operation. A23-A14 for the WS256N (A22-A14 for the WS128N, A21-A14 for the WS064N) are don't care during command sequence unlock cycles. CLK can be either VIL or VIH. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Configuration Register.
Figure 12.14
Asynchronous Program Operation Timings
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Program Command Sequence (last two cycles) tAVCH CLK tAS tAH tAVSC AVD# tAVDP Addresses 555h PA VA
Read Status Data
VA
In Progress
Data tCAS CE#
A0h
PD tDS tDH
Complete
OE#
tCSW tWP
tCH
WE# tWHWH1 tWPH tWC
tVCS VCC
Notes:
1. 2. 3. 4. 5. 6. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. In progress and complete refer to status of program operation. A23-A14 for the WS256N (A22-A14 for the WS128N, A21-A14 for the WS064N) are don't care during command sequence unlock cycles. Addresses are latched on the first rising edge of CLK. Either CE# or AVD# is required to go from low to high in between programming command sequences. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register. The Configuration Register must be set to the Synchronous Read Mode.
Figure 12.15
CE#
Synchronous Program Operation Timings
AVD# WE# Addresses Data Don't Care A0h
PA Don't Care PD Don't Care
OE# ACC
VID
tVIDS tVID
VIL or VIH
Note: Use setup and hold times from conventional program operation.
Figure 12.16 February 17, 2005 S75WS-N-00_A0
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AVD# tCE CE# tCH OE# tOEH WE# tACC Addresses VA VA
High Z
tCEZ
tOE
tOEZ
High Z
Data
Status Data
Status Data
Notes:
1. 2. Status reads in figure are shown as asynchronous. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is completeData# Polling outputs true data.
Figure 12.17
Data# Polling Timings (During Embedded Algorithm)
AVD# tCE CE# tCH OE# tOEH WE# tACC Addresses VA VA
High Z
tCEZ
tOE
tOEZ
Data
High Z
Status Data
Status Data
Notes:
1. 2. Status reads in figure are shown as asynchronous. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, .
Figure 12.18
Toggle Bit Timings (During Embedded Algorithm)
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CE#
CLK
AVD#
Addresses
VA
VA
OE#
tIACC tIACC Status Data Status Data
Data
RDY
Notes:
1. 2. 3. The timings are similar to synchronous read timings. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, . RDY is active with data (D8 = 1 in the Configuration Register). When D8 = 0 in the Configuration Register, RDY is active one clock cycle before data.
Figure 12.19
Enter Embedded Erasing WE#
Synchronous Data Polling Timings/Toggle Bit Timings
Erase Suspend Erase
Enter Erase Suspend Program Erase Suspend Program
Erase Resume Erase Suspend Read Erase Erase Complete
Erase Suspend Read
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to
toggle DQ2 and DQ6
Figure 12.20
DQ2 vs. DQ6
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Address boundary occurs every 128 words, beginning at address 00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.
C124 CLK Address (hex) AVD# 7C (stays high)
C125 7D
C126 7E
C127 7F
C127 7F
C128 80
C129 81
C130 82
C131 83
tRACC RDY(1) tRACC RDY(2)
latency latency
tRACC
tRACC
Data
D124
D125
D126
D127
D128
D129
D130
OE#, CE#
Notes:
1. 2. 3. 4. 5.
(stays low)
RDY(1) active with data (D8 = 1 in the Configuration Register). RDY(2) active one clock cycle before data (D8 = 0 in the Configuration Register). Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device not crossing a bank in the process of performing an erase or program. RDY does not go low and no additional wait states are required if the Burst frequency is <=66 MHz and the Boundary Crossing bit (D14) in the Configuration Register is set to 0
Figure 12.21
Latency with Boundary Crossing when Frequency > 66 MHz
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Address boundary occurs every 128 words, beginning at address 00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.
C124 CLK Address (hex) AVD# 7C (stays high)
C125 7D
C126 7E
C127 7F
C127 7F
tRACC RDY(1) tRACC RDY(2)
latency latency
tRACC
tRACC
Data
D124
D125
D126
D127
Read Status
OE#, CE#
Notes:
1. 2. 3. 4. 5.
(stays low)
RDY(1) active with data (D8 = 1 in the Configuration Register). RDY(2) active one clock cycle before data (D8 = 0 in the Configuration Register). Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device crossing a bank in the process of performing an erase or program. RDY does not go low and no additional wait states are required if the Burst frequency is < 66 MHz and the Boundary Crossing bit (D14) in the Configuration Register is set to 0.
Figure 12.22
Latency with Boundary Crossing into Program/Erase Bank
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Data
D0
D1
AVD#
Rising edge of next clock cycle following last wait state triggers next burst data total number of clock cycles following addresses being latched
OE# 1 CLK 0 1 2 3
4
5
6
7
2
3
4
5
number of clock cycles programmed
Wait State Configuration Register Setup:
D13, D13, D13, D13, D13, D13, D13, D13, D12, D12, D12, D12, D12, D12, D12, D12, D11 D11 D11 D11 D11 D11 D11 D11 = = = = = = = = 111 110 101 100 011 010 001 000 Reserved Reserved 5 programmed, 7 total 4 programmed, 6 total 3 programmed, 5 total 2 programmed, 4 total 1 programmed, 3 total 0 programmed, 2 total
Note: 6.Figure assumes address D0 is not at an address boundary, and wait state is set to 101
Figure 12.23 Example of Wait State Insertion
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Last Cycle in Program or Sector Erase Command Sequence
Read status (at least two cycles) in same bank and/or array data from other bank
Begin another write or program command sequence
tWC
tRC
tRC
tWC
CE#
OE# tOE tOEH WE# tWPH tWP tDS Data
PD/30h
tGHWL
tACC tDH
RD
tOEZ tOEH
RD AAh
tSR/W Addresses
PA/SA RA RA 555h
tAS AVD# tAH
Note: Breakpoints in waveforms indicate that system may alternately read array data from the non-busy bank while checking the status of the program or erase operation in the busy bank. The system should read status twice to ensure valid information.
Figure 12.24 Back-to-Back Read/Write Cycle Timings
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12.8.7
Erase and Programming Performance
Parameter Sector Erase Time 64 Kword 16 Kword VCC VCC VCC Chip Erase Time ACC VCC ACC VCC ACC VCC ACC VCC Chip Programming Time (Note 3) ACC
Notes:
1. 2. 3. 4. 5. 6. 7. 8. 9. Typical program and erase times assume the following conditions: 25C, 1.8 V VCC, 10,000 cycles; checkerboard data pattern. Under worst case conditions of 90C, VCC = 1.70 V, 100,000 cycles. Typical chip programming time is considerably less than the maximum chip programming time listed, and is based on utilizing the Write Buffer. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See the Appendix for further information about command definitions. Contact the local sales office for minimum cycling endurance values in specific applications and operating conditions. Refer to Application Note Erase Suspend/Resume Timing for more details. Word programming specification is based upon a single word programming operation not utilizing the write buffer. The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document is Preliminary for the S29W256N.
Typ (Note 1) 0.6 <0.15 153.6 (WS256N) 77.4 (WS128N) 39.3 (WS064N) 130.6 (WS256N) 65.8 (WS128N) 33.4 (WS064N) 40 24 9.4 6 300 192 157.3 (WS256N) 78.6 (WS128N) 39.3 (WS064N) 100.7 (WS256N) 50.3 (WS128N) 25.2 (WS064N)
Max (Note 2) 3.5 2 308 (WS256N) 154 (WS128N) 78 (WS064N)
Unit s
Comments
s 262 (WS256N) 132 (WS128N) 66 (WS064N) 400 240 94 60 3000 1920 314.6 (WS256N) 157.3 (WS128N) 78.6 (WS064N) 201.3 (WS256N) 100.7 (WS128N) 50.3 (WS064N) s
Excludes 00h programming prior to erasure (Note 4)
Single Word Programming Time (Note 8) Effective Word Programming Time utilizing Program Write Buffer Total 32-Word Buffer Programming Time
s
s
s
Excludes system level overhead (Note 5)
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12.8.8
BGA Ball Capacitance
Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ. 5.3 5.8 6.3 Max 6.3 6.8 7.3 Unit pF pF pF
Notes:
1. 2. 3. Sampled, not 100% tested. Test conditions TA = 25C; f = 1.0 MHz. The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document is Preliminary for the S29W256N.
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13 Appendix
This section contains information relating to software control or interfacing with the Flash device. For additional information and assistance regarding software, see the Additional Resources on page 19, or explore the Web at www.amd.com and www.fujitsu.com.
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Table 13.1
Cycles Command Sequence (Notes) Asynchronous Read (6) Reset (7) Manufacturer ID Device ID (9) Indicator Bits (10) Program Write to Buffer (11) Program Buffer to Flash Write to Buffer Abort Reset (12) Chip Erase Sector Erase Erase/Program Suspend (13) Erase/Program Resume (14) Set Configuration Register (18) Read Configuration Register CFI Query (15) Entry Program (16) CFI (16) Reset Entry Program (17) Read (17) Exit (17) First Addr Data RA RD XXX F0 555 AA 555 AA 555 555 555 SA 555 555 555 BA BA 555 555 [BA]555 555 XXX XXX XXX 555 555 00 555 AA AA AA 29 AA AA AA B0 30 AA AA 98 AA A0 98 90 AA AA Data AA
Memory Array Commands
Second Addr Data Bus Cycles (Notes 1-5) Third Fourth Addr Data Addr Data Fifth Addr Data Sixth Addr Data
Autoselect (8)
1 1 4 6 4 4 6 1 3 6 6 1 1 4 4 1 3 2 1 2 3 4 1 4
2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA
55 55 55 55 55 55 55 55
[BA]555 [BA]555 [BA]555 555 PA 555 555 555
90 90 90 A0 25 F0 80 80
[BA]X00 [BA]X01 [BA]X03 PA PA
0001 227E Data PD WC
BA+X0E
Data
BA+X0F
2200
PA
PD
WBL
PD
555 555
AA AA
2AA 2AA
55 55
555 SA
10 30
2AA 2AA 2AA PA XXX 2AA 2AA
55 55 55 PD 00 55 55
555 555 555
D0 C6 20
X00 X00
CR CR
Unlock Bypass Mode
Secured Silicon Sector
555 555
88 A0
PA
PD
2AA
55
555
90
XXX
00
Legend: X = Don't care. RA = Read Address. RD = Read Data. PA = Program Address. Addresses latch on the rising edge of the AVD# pulse or active edge of CLK, whichever occurs first. PD = Program Data. Data latches on the rising edge of WE# or CE# pulse, whichever occurs first. Notes: 1. See Table 8.1 for description of bus operations. 2. All values are in hexadecimal. 3. Shaded cells indicate read cycles. 4. Address and data bits not specified in table, legend, or notes are don't cares (each hex digit implies 4 bits of data). 5. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset command to return the device to reading array data. 6. No unlock or command cycles required when bank is reading array data. 7. Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information) or performing sector lock/unlock. 8. The system must provide the bank address. See Autoselect section for more information. 9. Data in cycle 5 is 2230 (WS256N), 2232 (WS064N), or 2231 (WS128N). 10. See Table 8.9 for indicator bit values.
SA = Sector Address. WS256N = A23-A14; WS128N = A22-A14; WS064N = A21-A14. BA = Bank Address. WS256N = A23-A20; WS128N = A22-A20; WS064N = A21-A18. CR = Configuration Register data bits D15-D0. WBL = Write Buffer Location. Address must be within the same write buffer page as PA. WC = Word Count. Number of write buffer locations to load minus 1. 11. Total number of cycles in the command sequence is determined by the number of words written to the write buffer. 12. Command sequence resets device for next command after writeto-buffer operation. 13. System may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation, and requires the bank address. 14. Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 15. Command is valid when device is ready to read array data or when device is in autoselect mode. Address equals 55h on all future devices, but 555h for WS256N/128N/064N. 16. Requires Entry command sequence prior to execution. Unlock Bypass Reset command is required to return to reading array data. 17. Requires Entry command sequence prior to execution. Secured Silicon Sector Exit Reset command is required to exit this mode; device may otherwise be placed in an unknown state. 18. Requires reset command to configure the Configuration Register.
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Table 13.2
Cycles Command Sequence (Notes) Command Set Entry (5) Lock Program (6, 12) Register Read (6) Bits Command Set Exit (7) Command Set Entry (5) Program [0-3] (8) Password Read (9) Protection Unlock Command Set Exit (7) Command Set Entry (5) PPB Program (10) Non-Volatile Sector All PPB Erase (10, 11) Protection (PPB) PPB Status Read Command Set Exit (7) Global Command Set Entry (5) Volatile Sector PPB Lock Bit Set Protection PPB Lock Bit Status Read Freeze Command Set Exit (7) (PPB Lock) Volatile Sector Protection (DYB) Command Set Entry (5) DYB Set DYB Clear DYB Status Read Command Set Exit (7) First Addr Data 555 AA XX A0 77 data XX 90 555 AA XX A0 0...00 PWD0 00 25 XX 90 555 AA XX A0 XX 80 SA RD(0) XX 90 555 AA XX A0 BA RD(0) XX 555 XX XX SA XX 90 AA A0 A0 RD(0) 90
Sector Protection Commands
Second Addr Data 2AA 55 77/00 data Bus Cycles (Notes 1-4) Third Fourth Fifth Addr Data Addr Data Addr Data 555 40 Sixth Addr Data Seventh Addr Data
3 2 1 2 3 2 4 7 2 3 2 2 1 2 3 2 1 2 3 2 2 1 2
XX 00 2AA 55 555 60 00 PWD[0-3] 0...01 PWD1 0...02 PWD2 00 03 00 PWD0 XX 00 2AA 55 [BA]555 C0 SA 00 00 30 XX 2AA XX XX 2AA SA SA XX 00 55 00 00 55 00 01 00 [BA]555 E0
0...03 PWD3 01 PWD1
02
PWD2
03
PWD3
00
29
[BA]555
50
Legend: X = Don't care. RA = Address of the memory location to be read. PD(0) = Secured Silicon Sector Lock Bit. PD(0), or bit[0]. PD(1) = Persistent Protection Mode Lock Bit. PD(1), or bit[1], must be set to `0' for protection while PD(2), bit[2] must be left as `1'. PD(2) = Password Protection Mode Lock Bit. PD(2), or bit[2], must be set to `0' for protection while PD(1), bit[1] must be left as `1'. PD(3) = Protection Mode OTP Bit. PD(3) or bit[3]. SA = Sector Address. WS256N = A23-A14; WS128N = A22-A14; WS064N = A21-A14. Notes: 1. All values are in hexadecimal. 2. Shaded cells indicate read cycles. 3. Address and data bits not specified in table, legend, or notes are don't cares (each hex digit implies 4 bits of data). 4. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset command to return the device to reading array data. 5. Entry commands are required to enter a specific mode to enable instructions only available within that mode. 6. If both the Persistent Protection Mode Locking Bit and the Password Protection Mode Locking Bit are set at the same time, the command operation aborts and returns the device to the default Persistent Sector Protection Mode during 2nd bus cycle. Note that on all future devices, addresses equal 00h, but is
BA = Bank Address. WS256N = A23-A20; WS128N = A22-A20; WS064N = A21-A18. PWD3-PWD0 = Password Data. PD3-PD0 present four 16 bit combinations that represent the 64-bit Password PWA = Password Address. Address bits A1 and A0 are used to select each 16-bit portion of the 64-bit entity. PWD = Password Data. RD(0), RD(1), RD(2) = DQ0, DQ1, or DQ2 protection indicator bit. If protected, DQ0, DQ1, or DQ2 = 0. If unprotected, DQ0, DQ1, DQ2 = 1. currently 77h for the WS256N only. See Table 9.1 and Table 9.2 for explanation of lock bits. Exit command must be issued to reset the device into read mode; device may otherwise be placed in an unknown state.
7. 8.
Entire two bus-cycle sequence must be entered for each portion of the password. 9. Full address range is required for reading password. 10. See Figure 9.2 for details. 11. The All PPB Erase command pre-programs all PPBs before erasure to prevent over-erasure. 12. The second cycle address for the lock register program operation is 77 for S29Ws256N; however, for WS128N and Ws064N this address is 00.
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13.1
Common Flash Memory Interface
The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified soft-ware algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and back-ward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address (BA)555h any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 13.3-13.6) within that bank. All reads outside of the CFI address range, within the bank, returns non-valid data. Reads from other banks are allowed, writes are not. To terminate reading CFI data, the system must write the reset command. The following is a C source code example of using the CFI Entry and Exit functions. Refer to the Spansion Low Level Driver User's Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines.
/* Example: CFI Entry command */ *( (UINT16 *)bank_addr + 0x555 ) = 0x0098; /* Example: CFI Exit command */ *( (UINT16 *)bank_addr + 0x000 ) = 0x00F0; /* write CFI entry command */
/* write cfi exit command
*/
For further information, please refer to the CFI Specification (see JEDEC publications JEP137-A and JESD68.01and CFI Publication 100). Please contact your sales office for copies of these documents.
Table 13.3
Addresses
10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah
CFI Query Identification String
Description
Query Unique ASCII string QRY Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists)
Data
0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h
Table 13.4
Addresses
1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h
System Interface String
Description
Data
0017h 0019h 0000h 0000h 0006h 0009h 000Ah 0000h 0004h 0004h 0003h 0000h VCC Min. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VCC Max. (write/erase) D7-D4: volt, D3-D0: 100 millivolt
VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present) Typical timeout per single byte/word write 2N s Typical timeout for Min. size buffer write 2N s (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported)
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Table 13.5
Addresses
27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch
Device Geometry Definition
Description
Data
0019h (WS256N) 0018h (WS128N) 0017h (WS064N) 0001h 0000h 0006h 0000h 0003h 0003h 0000h 0080h 0000h 00FDh (WS256N) 007Dh (WS128N) 003Dh (WS064N) 0000h 0000h 0002h 0003h 0000h 0080h 0000h 0000h 0000h 0000h 0000h
Device Size = 2N byte Flash Device Interface description (refer to CFI publication 100) Max. number of bytes in multi-byte write = 2N (00h = not supported) Number of Erase Block Regions within device Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100)
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
Table 13.6
Addresses
40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h
Primary Vendor-Specific Extended Query
Description
Data
0050h 0052h 0049h 0031h 0034h 0100h 0002h 0001h 0000h 0008h
Query-unique ASCII string PRI Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock (Bits 1-0), 0 = Required, 1 = Not Required Silicon Technology (Bits 5-2) 0100 = 0.11 m Erase Suspend, 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protect, 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 08 = Advanced Sector Protection
00F3h (WS256N) Simultaneous Operation 007Bh (WS128N) 003Fh (WS064N) Number of Sectors in all banks except boot bank 0001h 0000h 0085h 0095h 0001h 0001h
Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type, 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page, 04 = 16 Word Page ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag 0001h = Dual Boot Device Program Suspend. 00h = not supported
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Table 13.6
Addresses
51h 52h 53h 54h 55h 56h 57h 58h
Primary Vendor-Specific Extended Query (Continued)
Description Unlock Bypass, 00 = Not Supported, 01=Supported Secured Silicon Sector (Customer OTP Area) Size 2N bytes Hardware Reset Low Time-out during an embedded algorithm to read mode Maximum 2N ns Hardware Reset Low Time-out not during an embedded algorithm to read mode Maximum 2N ns Erase Suspend Time-out Maximum 2N ns Program Suspend Time-out Maximum 2N ns Bank Organization: X = Number of banks
Data
0001h 0007h 0014h 0014h 0005h 0005h 0010h
0013h (WS256N) 000Bh (WS128N) Bank 0 Region Information. X = Number of sectors in bank 0007h (WS064N) 0010h (WS256N) 0008h (WS128N) Bank 1 Region Information. X = Number of sectors in bank 0004h (WS064N) 0010h (WS256N) 0008h (WS128N) Bank 2 Region Information. X = Number of sectors in bank 0004h (WS064N) 0010h (WS256N) 0008h (WS128N) Bank 3 Region Information. X = Number of sectors in bank 0004h (WS064N) 0010h (WS256N) 0008h (WS128N) Bank 4 Region Information. X = Number of sectors in bank 0004h (WS064N) 0010h (WS256N) 0008h (WS128N) Bank 5 Region Information. X = Number of sectors in bank 0004h (WS064N) 0010h (WS256N) 0008h (WS128N) Bank 6 Region Information. X = Number of sectors in bank 0004h (WS064N) 0010h (WS256N) 0008h (WS128N) Bank 7 Region Information. X = Number of sectors in bank 0004h (WS064N) 0010h (WS256N) 0008h (WS128N) Bank 8 Region Information. X = Number of sectors in bank 0004h (WS064N) 0010h (WS256N) 0008h (WS128N) Bank 9 Region Information. X = Number of sectors in bank 0004h (WS064N) 0010h (WS256N) 0008h (WS128N) Bank 10 Region Information. X = Number of sectors in bank 0004h (WS064N) 0010h (WS256N) 0008h (WS128N) Bank 11 Region Information. X = Number of sectors in bank 0004h (WS064N) 0010h (WS256N) 0008h (WS128N) Bank 12 Region Information. X = Number of sectors in bank 0004h (WS064N) 0010h (WS256N) 0008h (WS128N) Bank 13 Region Information. X = Number of sectors in bank 0004h (WS064N) 0010h (WS256N) 0008h (WS128N) Bank 14 Region Information. X = Number of sectors in bank 0004h (WS064N) 0013h (WS256N) 000Bh (WS128N) Bank 15 Region Information. X = Number of sectors in bank 0007h (WS064N)
59h
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
60h
61h
62h
63h
64h
65h
66h
67h
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14 Commonly Used Terms
Term ACC Definition ACCelerate. A special purpose input signal which allows for faster programming or erase operation when raised to a specified voltage above VCC. In some devices ACC may protect all sectors when at a low voltage. Most significant bit of the address input [A23 for 256Mbit, A22 for128Mbit, A21 for 64Mbit] Least significant bit of the address input signals (A0 for all devices in this document). Operation where signal relationships are based only on propagation delays and are unrelated to synchronous control (clock) signal. Read mode for obtaining manufacturer and device information as well as sector protection status. Section of the memory array consisting of multiple consecutive sectors. A read operation in one bank, can be independent of a program or erase operation in a different bank for devices that offer simultaneous read and write feature. Smaller size sectors located at the top and or bottom of Flash device address space. The smaller sector size allows for finer granularity control of erase and protection for code or parameters used to initiate system operation after power-on or reset. Location at the beginning or end of series of memory locations. See synchronous read. 8 bits Common Flash Interface. A Flash memory industry standard specification [JEDEC 137A and JESD68.01] designed to allow a system to interrogate the Flash to determine its size, type and other performance parameters. Zero (Logic Low Level) Special purpose register which must be programmed to enable synchronous read mode Synchronous method of burst read whereby the device reads continuously until it is stopped by the host, or it has reached the highest address of the memory array, after which the read address wraps around to the lowest memory array address Returns bits of a Flash memory array to their default state of a logical One (High Level). Halts an erase operation to allow reading or programming in any sector that is not selected for erasure Ball Grid Array package. Spansion LLC offers two variations: Fortified Ball Grid Array and Fine-pitch Ball Grid Array. See the specific package drawing or connection diagram for further details. Synchronous (burst) read operation in which 8, 16, or 32 words of sequential data with or without wraparound before requiring a new initial address. Multi-Chip Package. A method of combining integrated circuits in a single package by stacking multiple die of the same or different devices. The programmable area of the product available for data storage. SpansionTM trademarked technology for storing multiple bits of data in the same transistor.
Amax Amin Asynchronous Autoselect
Bank
Boot sector Boundary Burst Read Byte CFI Clear Configuration Register
Continuous Read Erase Erase Suspend/Erase Resume
BGA
Linear Read MCP Memory Array MirrorBitTM Technology
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Term Page
Definition Group of words that may be accessed more rapidly as a group than if the words were accessed individually. Asynchronous read operation of several words in which the first word of the group takes a longer initial access time and subsequent words in the group take less page access time to be read. Different words in the group are accessed by changing only the least significant address lines. Sector protection method which uses a programmable password, in addition to the Persistent Protection method, for protection of sectors in the Flash memory device. Sector protection method that uses commands and only the standard core voltage supply to control protection of sectors in the Flash memory device. This method replaces a prior technique of requiring a 12V supply to control the protection method. Stores data into a Flash memory by selectively clearing bits of the memory array in order to leave a data pattern of ones and zeros. Halts a programming operation to read data from any location that is not selected for programming or erase. Host bus cycle that causes the Flash to output data onto the data bus. Dynamic storage bits for holding device control information or tracking the status of an operation. Secured Silicon. An area consisting of 256 bytes in which any word may be programmed once, and the entire area may be protected once from any future programming. Information in this area may be programmed at the factory or by the user. Once programmed and protected there is no way to change the secured information. This area is often used to store a software readable identification such as a serial number. Use of one or more control bits per sector to indicate whether each sector may be programmed or erased. If the Protection bit for a sector is set the embedded algorithms for program or erase ignores program or erase commands related to that sector. An Area of the memory array in which all bits must be erased together by an erase operation. Mode of operation in which a host system may issue a program or erase command to one bank, that embedded algorithm operation may then proceed while the host immediately follows the embedded algorithm command with reading from another bank. Reading may continue concurrently in any bank other than the one executing the embedded algorithm operation. Operation that progresses only when a timing signal, known as a clock, transitions between logic levels (that is, at a clock edge). Separate power supply or voltage reference signal that allows the host system to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data inputs. Mode that facilitates faster program times by reducing the number of command bus cycles required to issue a write operation command. In this mode the initial two Unlock write cycles, of the usual 4 cycle Program command, are not required - reducing all Program commands to two bus cycles while in this mode. Two contiguous bytes (16 bits) located at an even byte boundary. A double word is two contiguous words located on a two word boundary. A quad word is four contiguous words located on a four word boundary.
Page Read
Password Protection
Persistent Protection
Program Program Suspend/Program Resume Read Registers
Secured Silicon
Sector Protection
Sector
Simultaneous Operation
Synchronous Operation
VersatileIOTM (VIO)
Unlock Bypass
Word
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Term
Definition Special burst read mode where the read address wraps or returns back to the lowest address boundary in the selected range of words, after reading the last Byte or Word in the range, e.g. for a 4 word range of 0 to 3, a read beginning at word 2 would read words in the sequence 2, 3, 0, 1. Interchangeable term for a program/erase operation where the content of a register and or memory location is being altered. The term write is often associated with writing command cycles to enter or exit a particular mode of operation. Multi-word area in which multiple words may be programmed as a single operation. A Write Buffer may be 16 to 32 words long and is located on a 16 or 32 word boundary respectively. Method of writing multiple words, up to the maximum size of the Write Buffer, in one operation. Using Write Buffer Programming results in 8 times faster programming time than by using single word at a time programming commands. Allows the host system to determine the status of a program or erase operation by reading several special purpose register bits.
Wraparound
Write
Write Buffer
Write Buffer Programming
Write Operation Status
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S29RS512N
512 Megabit (32 M x 16-Bit) CMOS 1.8 Volt-only Read/Write, Burst Mode, Mass Storage Flash Memory for Multi-Chip Products (MCP)
DATA SHEET
Distinctive Characteristics
Architectural Advantages
Single 1.8 volt read, program and erase (1.65 to 1.95 volt) Manufactured on 0.11 m MirrorBitTM process Read/Write operation
-- Zero latency between read and write operations
Hardware Features
Sector Protection
-- Dynamic Protection Bits (DYB) are assigned to every sector -- A command sector protection to lock/unlock combinations of individual sectors to prevent/allow program or erase operations within that sector.
Programable Burst Interface
-- 2 Modes of Burst Read Operation -- Linear Burst: 8, 16, and 32 words with or without wrap-around -- Continuous Sequential Burst
Handshaking feature available
-- Provides host system with minimum possible latency by monitoring RDY
Sector Architecture
-- one-hundred-twenty-eight 256 Kword sectors
ACC input: Acceleration function reduces programming time in a factory setting Low VCC write inhibit
100,000 erase cycle per sector typical 20-year data retention typical
Software Features
Software command set compatible with JEDEC 42.4 standards Data# Polling and toggle bits
-- Provides a software method of detecting program and erase operation completion
Performance Charcteristics
Read access times at 80/66/54 MHz
-- Burst access times of 9.1/11.2/13.5 ns -- Synchronous latency of 148 ns -- Asynchronous random access times of 143 ns
Erase Suspend/Resume
-- Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation
High Performance
-- Typical word programming time of 40 s -- Typical effective word programming time of 9.4 s utilizing a 32-Word Write Buffer at Vcc Level -- Typical effective word programming time of 6 s utilizing a 32-Word Write Buffer at ACC Level -- Typical 2 s sector erase time for 256 Kword sectors
Program Suspend/Resume
-- Suspends a programming operation to read data from a sector other than the one being programmed, then resume the programming operation
Power dissipation (typical values, CL = 30 pF) @ 80 MHz
-- -- -- -- Continuous Burst Mode Read: 35 mA Program: 19 mA Erase: 19 mA Standby mode: 20 A
Unlock Bypass Program command
-- Reduces overall programming time when issuing multiple program command sequences
Additional Features
Program Operation
-- Ability to perform synchronous and asynchronous write operation independent of burst control register setting
Publication Number S75WS-N-00
Revision A
Amendment 0
Issue Date February 17, 2005
Data
Sheet
General Description
The S29RS512N is a 512 Mbit, 1.8 Volt-only, simultaneous Read/Write, Burst Mode Flash memory device, organized as 33,554,432words of 16 bits each. This device uses a single VCC of 1.65 to 1.95 V to read, program, and erase the memory array. A 9.0-volt VHH on ACC may be used for faster program performance in a factory setting environment. The device uses Chip Enable (CE#), Write Enable (WE#), Address Valid (AVD#) and Output Enable (OE#) to control asynchronous read and write operations. For burst operations, the device additionally requires Ready (RDY), and Clock (CLK). This implementation allows easy interface with minimal glue logic to a wide range of microprocessors/microcontrollers for high performance read operations. The burst read mode feature gives system designers flexibility in the interface to the device. The user can preset the burst length and then wrap or non-wrap through the same memory space, or read the currently addressable flash array block in continuous mode. The rising clock edge initiates burst accesses and determines when data will be output. The device is entirely command set compatible with the JEDEC 42.4 single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timing. Register contents serve as inputs to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm - an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster program times by requiring only two write cycles to program data instead of four. Additionally, Write Buffer Programming is available on this family of devices. This feature provides superior programming performance by grouping locations being programmed. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm - an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The Program Suspend/Program Resume feature enables the user to put program on hold to read data from any sector that is not selected for programming. If a read is needed from the Dynamic Protection area after a program suspend, then the user must use the proper command sequence to enter and exit this region. The program suspend/resume functionality is also available when programming in erase suspend (1 level depth only). The Erase Suspend/Erase Resume feature enables the user to put erase on hold to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from the Dynamic Protection area, after an erase suspend, then the user must use the proper command sequence to enter and exit this region. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read boot-up firmware from the Flash memory device. The host system can detect whether a memory array program or erase operation is complete by using the device status bit DQ7 (Data# Polling), DQ6/DQ2 (toggle bits), DQ5 (exceeded timing limit), DQ3 (sector erase start timeout state indicator), and DQ1 (write to buffer abort). After a program or erase cycle has been completed, the device automatically returns to reading array data.
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The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors [The device is fully erased when shipped from the factory]. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. When the ACC pin = VIL, the entire flash memory array is protected. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both modes. Spansion's Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector. The data is programmed using hot electron injection.
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15 Product Selector Guide
S29RS512N Synchronous/Burst Speed Option Max Latency, ns (tIACC) Max Burst Access Time, ns (tBACC) Max OE# Access, ns (tOE) 80 MHz 148 9.1 9.1 66 MHz 160 11.2 11.2 54 MHz 160 13.5 13.5 Asynchronous Max Access Time, ns (tACC) Max CE# Access, ns (tCE) Max OE# Access, ns (tOE) 143 148 9.1
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16 Block Diagram
VCC VSS RDY Buffer RDY Erase Voltage Generator Input/Output Buffers DQ15-DQ0
WE# RESET# ACC
State Control Command Register
PGM Voltage Generator Chip Enable Output Enable Logic Data Latch
CE# OE#
Y-Decoder VCC Detector
Y-Gating
Address Latch
Timer
X-Decoder
Cell Matrix
AVD# CLK
Burst State Control
Burst Address Counter
Amax-A0* Amax = A24
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17 Logic Symbol
25 or 24 Amax- CLK DQ15-DQ0 16
ACC CE# OE# WE# RESET# AVD# RDY
Note: Amax = A24 for 512Mb.
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18 Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 18.1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.
Table 18.1
Operation Asynchronous Read - Addresses Latched Asynchronous Read - Addresses Steady State Asynchronous Write Synchronous Write Standby (CE#) Hardware Reset Burst Read Operations Load Starting Burst Address Advance Burst to next address with appropriate Data presented on the Data Bus Terminate current Burst read cycle Terminate current Burst read cycle via RESET# Terminate current Burst read cycle and start new Burst read cycle L L H X L CE# L L L L H X
Device Bus Operations
OE# L L H H X X WE# H H L L X X Addresses Addr In Addr In Addr In Addr In X X DQ15-0 I/O I/O I/O I/O HIGH Z HIGH Z RESET# H H H H H L X X X X CLK X X X L L AVD#
X L X X X
H H H H H
Addr In X X X Addr In
X Burst Data Out HIGH Z HIGH Z I/O
H H H L H X H X X
Legend: L = Logic 0, H = Logic 1, X = Don't Care.
18.1
Requirements for Asynchronous Read Operation (Non-Burst)
To read data from the memory array, the system must first assert a valid address on Amax-A0, while driving AVD# and CE# to VIL. WE# should remain at VIH. The rising edge of AVD# latches the address. The data will appear on DQ15-DQ0. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from the stable CE# to valid data at the outputs. The output enable access time (tOE) is the delay from the falling edge of OE# to valid data at the output. The internal state machine is set for reading array data in asynchronous mode upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition.
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18.2
Requirements for Synchronous (Burst) Read Operation
The device is capable of continuous sequential burst operation and linear burst operation of a preset length. When the device first powers up, it is enabled for asynchronous read operation. Prior to entering burst mode, the system should determine how many wait states are desired for the initial word (tIACC) of each burst access, what mode of burst operation is desired and how the RDY signal will transition with valid data. The system would then write the configuration register command sequence. See Set Configuration Register Command Sequence for further details. Table 2-4 shows the address latency scheme for varying frequencies.
Table 18.2
Initial Addr 00 01 10 11 X D0 D1 D2 D3 X+1 D1 D2 D3 1ws
Address Latency Scheme for < 56Mhz
Cycle X+2 D2 D3 1ws 1ws X+3 D3 1ws 1ws 1ws Add ws 0ws 0ws 0ws 0ws X+4 D4 D4 D4 D4 X+5 D5 D5 D5 D5 X+6 D6 D6 D6 D6
Table 18.3
Initial Addr 00 01 10 11 X D0 D1 D2 D3 X+1 D1 D2 D3 1ws
Address Latency Scheme for < 70Mhz
Cycle X+2 D2 D3 1ws 1ws X+3 D3 1ws 1ws 1ws Add ws 1ws 1ws 1ws 1ws X+4 D4 D4 D4 D4 X+5 D5 D5 D5 D5 X+6 D6 D6 D6 D6
Table 18.4
Initial Addrs 00 01 10 11 X D0 D1 D2 D3 X+1 D1 D2 D3 1ws
Address Latency Scheme for < 84Mhz
Cycle X+2 D2 D3 1ws 1ws X+3 D3 1ws 1ws 1ws Add ws 2ws 2ws 2ws 2ws X+4 D4 D4 D4 D4 X+5 D5 D5 D5 D5 X+6 D6 D6 D6 D6
Address Latency Scheme for < 84Mhz The initial word is output tIACC after the rising edge of the first CLK cycle. Subsequent words are output tBACC after the rising edge of each successive clock cycle, which automatically increments the internal address counter. Note that the device has a fixed internal address boundary that occurs every 512 words and there is a boundary crossing latency of 4/8 wait states, when the device is operating at frequencies lower than 56/80Mhz respectively. During the time the device is outputting data with the starting burst address not divisible by four, additional waits are required. For example, if the device is operating at frequency of 80Mhz and if the starting burst address is divisible by four A1:0 = 00, two additional wait state is required.
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If the starting burst address is at address A1:0 = 01, 10, 11 then three, four or five wait states are required, respectively, until data D4 is read and burst sequence becomes linear. Please refer to Table 18.4 for further details. The RDY output indicates this condition to the system by deasserting.
18.2.1
Continuous Burst
The device will continue to output sequential burst data, wrapping around to address 000000h after it reaches the highest addressable memory location, until the system drives CE# high, RESET# low, or AVD# low in conjunction with a new address. See Table 18.1.
18.2.2
8-, 16-, and 32-Word Linear Burst with Wrap Around
The remaining three modes are of the linear wrap around design, in which a fixed number of words are read from consecutive addresses. In each of these modes, the burst addresses read are determined by the group within which the starting address falls. The groups are sized according to the number of words read in a single burst sequence for a given mode (see Table 18.5.).
Table 18.5
Mode 8-word 16-word 32-word Group Size 8 words 16 words 32 words
Burst Address Groups
Group Address Ranges 0-7h, 8-Fh, 10-17h,... 0-Fh, 10-1Fh, 20-2Fh,... 00-1Fh, 20-3Fh, 40-5Fh,...
As an example: if the starting address in the 8-word mode is 3ch, the address range to be read would be 38-3Fh, and the burst sequence would be 3C, 3D, 3E, 3F, 38, 39, 3A, 3Bh. if wrap around is enable. The burst sequence begins with the starting address written to the device, but wraps back to the first address in the selected group and stops at the group size, terminating the burst read. In a similar fashion, the 16-word and 32-word Linear Wrap modes begin their burst sequence on the starting address written to the device, and then wrap back to the first address in the selected address group. Note that in these three burst read modes the address pointer does not cross the boundary that occurs every 512 words; thus, no wait states are inserted (except during the initial access). (see Figure 25.4)
18.2.3
8-, 16-, and 32-Word Linear Burst without Wrap Around
If wrap around is not enabled, 8-word, 16-word, or 32-word burst will execute linearly up to word boundary. The burst will stop after 8, 16, or 32 addresses and will not wrap around to the first address of the selected group. As an example: if the starting address in the 8-word mode is 3ch, the address range to be read would be 39-40h, and the burst sequence would be 3C, 3D-3E-3F40-41-42-43h if wrap around is not enabled. The next address to be read will require a new address and AVD# pulse. The address range would stay within the address block, causing address FFFFh to be followed by 0000h. Note that in this burst mode, the address pointer may cross the boundary that occurs every 128 words.
18.3
Configuration Register
The device uses a configuration register to set the various burst parameters: number of wait states, burst read mode, RDY configuration, and synchronous mode active.
18.4
RDY: Ready
The RDY is a dedicated output that, when the device is configured in the Synchronous mode, indicates (when at logic low) the system should wait 1 clock cycle before expecting the next word of data. The RDY pin is only controlled by CE#. Using the RDY Configuration Command Sequence, RDY can be set so that a logic low indicates the system should wait 2 clock cycles before expecting valid data.
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The following conditions cause the RDY output to be low: during the initial access (in burst mode), and at the boundary crossing, that occurs every 512 words beginning with address 1FFh.
18.5
Handshaking
The device is equipped with a handshaking feature that allows the host system to simply monitor the RDY signal from the device to determine when the burst data is ready to be read. The host system should use the programmable wait state configuration to set the number of wait states for optimal burst mode operation. The initial word of burst data is indicated by the rising edge of RDY after OE# goes low. For optimal burst mode performance, the host system must set the appropriate number of wait states in the flash device depending on clock frequency. See Set Configuration Register Command Sequence and Requirements for Synchronous (Burst) Read Operation for more information.
18.6
Writing Commands/Command Sequences
The device has the capability of performing an asynchronous or synchronous write operation. While the device is configured in Asynchronous read it is able to perform Asynchronous write operations only. CLK is ignored when the device is configured in the Asynchronous mode. When in the Synchronous read mode configuration, the device is able to perform both Asynchronous and Synchronous write operations. CLK and AVD# address latch is supported in the Synchronous programming mode. During a synchronous write operation, to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive AVD# and CE# to VIL, and OE# to VIH when providing an address to the device, and drive WE# and CE# to VIL, and OE# to VIH. when writing commands or data. During an asynchronous write operation, the system must drive CE# and WE# to VIL and OE# to VIH when providing an address, command, and data. Addresses are latched on the last falling edge of WE# or CE#, while data is latched on the 1st rising edge of WE# or CE# (see ). The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word, instead of four. An erase operation can erase one sector, multiple sectors or the entire device. Table 19.6 indicates the address space that each sector occupies. A sector address is the address bits required to uniquely select a sector. ICC2 in the DC Characteristics section represents the active current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations.
18.7
Accelerated Program/Chip Erase Operations
The device offers accelerated program and accelerated chip erase operations through the ACC functionACC is intended to allow faster manufacturing throughput at the factory and not to be used in system operations. The system can use the Write Buffer Load command sequence. Note that if a Write-to-BufferAbort Reset is required, the full 3-cycle RESET command sequence must be used to reset the device. Removing VHH from the ACC input, upon completion of the embedded program or erase operation, returns the device to normal operation. Note that sectors must be unlocked prior to raising ACC to VHH. When at VIL, ACC locks all sectors. ACC should be at VIH for all other conditions. number loaded = the number of locations to program minus 1. For example, if the system will program 6 address locations, then 05h should be written to the device.)
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The system then writes the starting address/data combination. This starting address is the first address/data pair to be programmed, and selects the write-buffer-page address. All subsequent address/data pairs must fall within the selected-write-buffer-page where Amax = 24 for RS512N. The write-buffer-page is selected by addresses Amax - A5. The write-buffer-page addresses must be the same for all address/data pairs loaded into the write buffer. (This means Write Buffer Programming cannot be performed across multiple write-buffer-pages. This also means that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load programming data outside of the selected writebuffer-page, the operation will ABORT.) After writing the Starting Address/Data pair, the system then writes the remaining address/data paris into the write buffer. Write buffer locations may be loaded in any order. Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter will be decremented for every data load operation. Also, the last data loaded at a location before the Program Buffer to Flash confirm command will be programmed into the device. It is the software's responsibility to comprehend ramifications of loading a write-buffer location more than once. The counter decrements for each data load operation, not for each unique writebuffer-address location. Once the specified number of write buffer locations have been loaded, the system must then write the Program Buffer to Flash command at the Sector Address. Any other address/data write combinations will abort the Write Buffer Programming operation. The device then goes busy. The Data Bar polling techniques should be used while monitoring the last address location loaded into the write buffer. This eliminates the need to store an address in memory because the system can load the last address location, issue the program confirm command at the last loaded address location, and then data bar poll at that same address. DQ7, DQ6, DQ5, DQ2, and DQ1 should be monitored to determine the device status during Write Buffer Programming. The write-buffer embedded programming operation can be suspended using the standard suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device will return to READ mode. The Write Buffer Programming Sequence can be ABORTED in the following ways: Load a value that is greater than the page buffer size during the Number of Locations to Program step. Write to an address in a sector different than the one specified during the Write-Buffer-Load command. Write an Address/Data pair to a different write-buffer-page than the one selected by the Starting Address during the write buffer data loading stage of the operation. Write data other than the Confirm Command after the specified number of data load cycles. The ABORT condition is indicated by DQ1 = 1, DQ7 = Data# (for the last address location loaded), DQ6 = TOGGLE, DQ5 = 0. This indicates that the Write Buffer Programming Operation was ABORTED. A Write-to-Buffer-Abort reset command sequence is required when using the WriteBuffer-Programming features in Unlock Bypass mode. [Use of the write buffer is strongly recommended for programming when multiple words are to be programmed.] from the internal register (which is separate from the memory array)
18.8
Dynamic Sector Protection
The device offers data protection at the sector level and the DYB associated command sequences disables or re-enables both program and erase operations in any sector or sector group. Dynamically Locked--The sector is protected and can be changed by a simple command Unlocked--The sector is unprotected and can be changed by a simple command
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18.8.1
Dynamic Protection Bit (DYB)
A volatile protection bit is assigned for each sector. After power-up or hardware reset, the contents of all DYBs is cleared erased to 1. In other words, the DYB powers-up in an unprotected state. Each DYB is individually modifiable through the DYB Write Command. The Protection State for each sector is determined by the DYB related to that sector. The DYBs control whether or not the sector is protected or unprotected. By issuing the DYB Write command sequences, the DYBs will be set (programmed to 0) or cleared (erased to 1), thus placing each sector in the protected or unprotected state. These are the so-called Dynamic Locked or Unlocked states. They are called dynamic states because it is very easy to switch back and forth between the protected and unprotected conditions. This allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. The DYBs maybe set or cleared as often as needed.
18.9
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# inputs are both held at VCC. The device requires standard access time (tCE) for read access, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 in the DC Characteristics section represents the standby current specification.
18.10 Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. While in asynchronous mode, the device automatically enables this mode when addresses remain stable for tACC + 20 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. While in synchronous mode, the Automatic Sleep Mode is disabled. Note that a new burst operation is required to provide new data. ICC6 in the DC Characteristics section represents the automatic sleep mode current specification.
18.11 RESET#: Hardware Reset Input
The RESET# input provides a hardware method of resetting the device to reading array data. When RESET# is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/ write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS, the standby current will be greater. RESET# may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted tRP operation, the device requires a time of tRH + tRP before the device is ready to read data again. If RESET# is asserted when a program or erase operation is not executing, the reset operation is completed within a time of tRP (not during Embedded Algorithms). The system can read data tRH after RESET# returns to VIH.
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Refer to the Synchronous/Burst Read section for RESET# parameters and to Figure 25.9 for the timing diagram.
18.12 Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The outputs are placed in the high impedance state.
18.13 Hardware Data Protection
The following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise.
18.13.1 Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control inputs to prevent unintentional writes when VCC is greater than VLKO.
18.13.2 Write Pulse Glitch Protection
Noise pulses do not initiate a write cycle.
18.13.3 Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one.
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19 Sector Address / Memory Address Map
Table 19.6
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 Sector Size 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords
Sector Address / Memory Address Map for the RS512N
(A24-A0) Address Range 0000000h-003FFFFh 0040000h-007FFFFh 0080000h-00BFFFFh 00C0000h-00FFFFFh 0100000h-013FFFFh 0140000h-017FFFFh 0180000h-01BFFFFh 01C0000h-01FFFFFh 0200000h-023FFFFh 0240000h-027FFFFh 0280000h-02BFFFFh 02C0000h-02FFFFFh 0300000h-033FFFFh 0340000h-037FFFFh 0380000h-03BFFFFh 03C0000h-03FFFFFh 0400000h-043FFFFh 0440000h-047FFFFh 0480000h-04BFFFFh 04C0000h-04FFFFFh 0500000h-053FFFFh 0540000h-057FFFFh 0580000h-05BFFFFh 05C0000h-05FFFFFh 0600000h-063FFFFh 0640000h-067FFFFh 0680000h-06BFFFFh 06C0000h-06FFFFFh 0700000h-073FFFFh 0740000h-077FFFFh 0780000h-07BFFFFh 07C0000h-07FFFFFh 0800000h-083FFFFh 0840000h-087FFFFh 0880000h-08BFFFFh 08C0000h-08FFFFFh 0900000h-093FFFFh 0940000h-097FFFFh 0980000h-09BFFFFh 09C0000h-09FFFFFh Sector SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 Sector Size 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords (A24-A0) Address Range 1000000h-103FFFFh 1040000h-107FFFFh 1080000h-10BFFFFh 10C0000h-10FFFFFh 1100000h-113FFFFh 1140000h-117FFFFh 1180000h-11BFFFFh 11C0000h-11FFFFFh 1200000h-123FFFFh 1240000h-127FFFFh 1280000h-12BFFFFh 12C0000h-12FFFFFh 1300000h-133FFFFh 1340000h-137FFFFh 1380000h-13BFFFFh 13C0000h-13FFFFFh 1400000h-143FFFFh 1440000h-147FFFFh 1480000h-14BFFFFh 14C0000h-14FFFFFh 1500000h-153FFFFh 1540000h-157FFFFh 1580000h-15BFFFFh 15C0000h-15FFFFFh 1600000h-163FFFFh 1640000h-167FFFFh 1680000h-16BFFFFh 16C0000h-16FFFFFh 1700000h-173FFFFh 1740000h-177FFFFh 1780000h-17BFFFFh 17C0000h-17FFFFFh 1800000h-183FFFFh 1840000h-187FFFFh 1880000h-18BFFFFh 18C0000h-18FFFFFh 1900000h-193FFFFh 1940000h-197FFFFh 1980000h-19BFFFFh 19C0000h-19FFFFFh
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Table 19.6
Sector SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 Sector Size
Sector Address / Memory Address Map for the RS512N (Continued)
(A24-A0) Address Range 0A00000h-0A3FFFFh 0A40000h-0A7FFFFh 0A80000h-0ABFFFFh 0AC0000h-0AFFFFFh 0B00000h-0B3FFFFh 0B40000h-0B7FFFFh 0B80000h-0BBFFFFh 0BC0000h-0BFFFFFh 0C00000h-0C3FFFFh 0C40000h-0C7FFFFh 0C80000h-0CBFFFFh 0CC0000h-0CFFFFFh 0D00000h-0D3FFFFh 0D40000h-0D7FFFFh 0D80000h-0DBFFFFh 0DC0000h-0DFFFFFh 0E00000h-0E3FFFFh 0E40000h-0E7FFFFh 0E80000h-0EBFFFFh 0EC0000h-0EFFFFFh 0F00000h-0F3FFFFh 0F40000h-0F7FFFFh 0F80000h-0FBFFFFh 0FC0000h-0FFFFFFh Sector SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 Sector Size 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords (A24-A0) Address Range 1A00000h-1A3FFFFh 1A40000h-1A7FFFFh 1A80000h-1ABFFFFh 1AC0000h-1AFFFFFh 1B00000h-1B3FFFFh 1B40000h-1B7FFFFh 1B80000h-1BBFFFFh 1BC0000h-1BFFFFFh 1C00000h-1C3FFFFh 1C40000h-1C7FFFFh 1C80000h-1CBFFFFh 1CC0000h-1CFFFFFh 1D00000h-1D3FFFFh 1D40000h-1D7FFFFh 1D80000h-1DBFFFFh 1DC0000h-1DFFFFFh 1E00000h-1E3FFFFh 1E40000h-1E7FFFFh 1E80000h-1EBFFFFh 1EC0000h-1EFFFFFh 1F00000h-1F3FFFFh 1F40000h-1F7FFFFh 1F80000h-1FBFFFFh 1FC0000h-1FFFFFFh
256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords
19.1
Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data in asynchronous mode. The device is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector within the same device. After completing a programming operation in the Erase Suspend mode, the system may once again read array data from any non-erase-suspended sector within the same device. See the Erase Suspend/Erase Resume Commands section for more information. After the device accepts a Program Suspend command, the device enters the program-suspendread mode, after which the system can read data from any non-program-suspended sector within the device. See Program Suspend/Program Resume Commands for more information. The system must issue the reset command to return device to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation, or if the device is in the autoselect mode. See the Reset Command section for more information. If DQ1 goes high during Write Buffer Programming, the system must issue the Write Buffer Abort Reset command.
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See also the Requirements for Asynchronous Read Operation (Non-Burst) and the Requirements for Synchronous (Burst) Read Operation sections for more information. The Asynchronous Read and Synchronous/Burst Read tables provide the read parameters, Figure 25.2, Figure 25.3, and Figure 25.7 show the timings.
19.2
Set Configuration Register Command Sequence
The device uses a configuration register to set the various burst parameters: number of wait states, burst read mode, RDY configuration, and synchronous mode active. The configuration register must be set before the device will enter burst mode. The configuration register is loaded with a four-cycle command sequence. The first two cycles are standard unlock sequences. On the third cycle, the data should be D0h and address bits should be 555h. During the fourth cycle, the configuration code should be entered onto the data bus with the address bus set to address 000h or 001h. Once the data has been programmed into the configuration register, a software reset command is required to set the device into the correct state. The device will power up or after a hardware reset with the default setting, which is in asynchronous mode. The register must be set before the device can enter synchronous mode. The configuration register can not be changed during device operations (program, erase, or sector lock).
19.3
Read Configuration Register Command Sequence
The configuration register can be read with a four-cycle command sequence. The first two cycles are standard unlock sequences. On the third cycle, the data should be C6h and address bits should be 555h. During the fourth cycle, the configuration code should be read out of the data bus with the address bus set to address 000h or 001h. Once the data has been read from the configuration register, a software reset command is required to set the device into array read mode.
Power-up/ Hardware Reset
Asynchronous Read Mode Only
Set Burst Mode Configuration Register Command for Synchronous Mode (D15 = 0)
Set Burst Mode Configuration Register Command for Asynchronous Mode (D15 = 1)
Synchronous Read Mode Only
Figure 19.1
Synchronous/Asynchronous State Diagram
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19.3.1
Read Mode Setting
On power-up or hardware reset, the device is set to be in asynchronous read mode. This setting allows the system to enable or disable burst mode during system operations. Configuration Bit CR0.15 determines this setting: 1 for asynchronous mode, 0 for synchronous mode.
19.3.2
Programmable Wait State Configuration
The programmable wait state feature informs the device of the number of clock cycles that must elapse after AVD# is driven active before data will be available. This value is determined by the input frequency of the device. Configuration Bit CR1.0 & CR0.13-CR0.11 determine the setting (see Table 19.7). The wait state command sequence instructs the device to set a particular number of clock cycles for the initial access in burst mode. The number of wait states that should be programmed into the device is directly related to the clock frequency.
Table 19.7
CR1.0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CR0.13 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CR0.12 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
Programmable Wait State Settings
CR0.11 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Total Initial Access Cycles Reserved 3 4 5 6 7 Reserved Reserved 8 9 10 11 12 (default) 13 Reserved Reserved
Notes:
1. 2. Upon power-up or hardware reset, the default setting is twelve wait states. All other but setting are reserved.
It is recommended that the wait state command sequence be written, even if the default wait state value is desired, to ensure the device is set as expected. A hardware reset will set the wait state to the default setting.
19.3.3
Programmable Wait State
The host system should set CR1.0 & CR0.13-CR0.11 to 1100/1010/1000 for a clock frequency of 80/66/54 MHz for the system/device to execute at maximum speed.
19.3.4
Boundary Crossing Latency
Additional wait states must be inserted to account for boundary crossing latency. This is done by setting CR0.14 to a `1' (default). If required, CR0.14 can be changed to a `0' to remove the boundary crossing latency.
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19.3.5
Handshaking
For optimal burst mode performance, the host system must set the appropriate number of wait states in the flash device depending on the clock frequency. The autoselect function allows the host system to determine whether the flash device is enabled for handshaking. See the Autoselect Command Sequence for more information.
19.3.6
Burst Length Configuration
The device supports four different read modes: continuous mode, and 8, 16, and 32 word linear with or without wrap around modes. A continuous sequence (default) begins at the starting address and advances the address pointer until the burst operation is complete. If the highest address in the device is reached during the continuous burst read mode, the address pointer wraps around to the lowest address. For example, an eight-word linear read with wrap around begins on the starting address written to the device and then advances to the next 8 word boundary. The address pointer then returns to the 1st word after the previous eight word boundary, wrapping through the starting location. The sixteen- and thirty-two linear wrap around modes operate in a fashion similar to the eightword mode. Table 19.8 shows the CR0.2-CR0.0 and settings for the four read modes.
Table 19.8
Burst Length Configuration
Address Bits
Burst Modes Continuous 8-word linear 16-word linear 32-word linear
CR0.2 0 0 0 1
CR0.1 0 1 1 0
CR0.0 0 0 1 0
Note: Upon power-up or hardware reset the default setting is continuous.
19.3.7
Burst Wrap Around
By default, the device will perform burst wrap around with CR0.3 set to a `1'. Changing the CR0.3 to a `0' disables burst wrap around.
19.3.8
RDY Configuration
By default, the device is set so that the RDY pin will output VOH whenever there is valid data on the outputs. The device can be set so that RDY goes active one data cycle before active data. CR0.8 determines this setting; 1 for RDY active (default) with data, 0 for RDY active one clock cycle before valid data.
19.3.9
RDY Polarity
By default, the RDY pin will always indicate that the device is ready to handle a new transaction with CR0.10 set to a `1'. In this case, the RDY pin is active high. Changing the CR0.10 to a `0' sets the RDY pin to be active low. In this case, the RDY pin will always indicate that the device is ready to handle a new transaction when low.
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19.4
Configuration Register
Table 19.9 shows the address bits that determine the configuration register settings for various device functions.
Table 19.9
CR0. Bit CR0.15 CR0.14 Function Set Device Read Mode Boundary Crossing
Configuration Register
Settings (Binary)
0 = Synchronous Read (Burst Mode) Enabled 1 = Asynchronous Mode (default) 0 = No extra boundary crossing latency 1 = With extra boundary crossing latency (default) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 = = = = = = = = = = = = = = = = Reserved Data is valid Data is valid Data is valid Data is valid Data is valid Reserved Reserved Data is valid Data is valid Data is valid Data is valid Data is valid Data is valid Reserved Reserved on on on on on the the the the the 4th 5th 6th 7th 8th active active active active active CLK CLK CLK CLK CLK edge edge edge edge edge after after after after after addresses addresses addresses addresses addresses are are are are are latched latched latched latched latched
CR1.0 Programmable Wait State
on on on on on on
the the the the the the
9th active CLK edge after addresses are latched 10th active CLK edge after addresses are latched 11th active CLK edge after addresses are latched 12th active CLK edge after addresses are latched 13th active CLK edge after addresses are latched (default) 14th active CLK edge after addresses are latched
CR0.13 CR0.12 CR0.11 CR0.10 CR0.9 CR0.8 CR0.7 CR0.6 CR0.5 CR0.4 CR0.3 RDY Polarity Reserved RDY Reserved Reserved Reserved Reserved Burst Wrap Around 0 = RDY signal is active low 1 = RDY signal is active high (default) 1 = default 0 = RDY active one clock cycle before data 1 = RDY active with data (default) 1 = default 1 = default 0 = default 0 = default 0 = No Wrap Around Burst 1 = Wrap Around Burst (default) 000 = Continuous (default) 010 = 8-Word Linear Burst 011 = 16-Word Linear Burst 100 = 32-Word Linear Burst (All other bit settings are reserved)
CR0.2 Burst Length CR0.1 CR0.0
Note: 3.Device will be in the default state upon power-up or hardware reset.
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19.5
Reset Command
Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don't cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to which the system was writing to the read mode. [Once erasure begins, however, the device ignores reset commands until the operation is complete]. The reset command may be written between the sequence cycles in a program command sequence before programming begins (prior to the third cycle). This resets the device to which the system was writing to the read mode. If the program command sequence is written to the device that is in the Erase Suspend mode, writing the reset command returns the device to the erasesuspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a device entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that device to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in Erase Suspend and program-suspend-read mode if the device was in Program Suspend). Note: If DQ1 goes high during a Write Buffer Programming operation, the system must write the Write to Buffer Abort Reset command sequence to RESET the device to reading array data. The standard RESET command will not work. See Table 19.9 for details on this command sequence.
19.6
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. The Command Definitions table shows the address and data requirements. The autoselect command sequence may be written to an address within the device that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the autoselect command. The device then enters the autoselect mode. No subsequent data will be made available if the autoselect data is read in synchronous mode. The system may read at any address within the device any number of times without initiating another autoselect command sequence. The following table describes the address requirements for the various autoselect functions, and the resulting data. The device ID is read in three cycles.
Table 19.10
Description
Manufacturer ID Device ID, Word 1 Device ID, Word 2 Device ID, Word 3 Indicator Bits
Autoselect Addresses
Read Data
01h 227Eh 2229 (RS512N) 2201 (RS512N) DQ15 - DQ5 = 0 DQ4 & DQ3 = 11 DQ2 - DQ0 = 0
Address
00h 01h 0Eh 0Fh 03h
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The system must write the reset command to return to the read mode (or erase-suspend-read mode if the device was previously in Erase Suspend).
19.7
Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. The Command Definitions table shows the address and data requirements for the program command sequence. When the Embedded Program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by monitoring DQ7 or DQ6/DQ2. Refer to the "Write Operation Status" section for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from 0 back to a 1. Only erase operations can convert a 0 back to a 1. Attempting to program a 1 over a 0 will result in a programming failure.
Note: See the Command Definitions table for program command sequence.
Figure 19.2 Program Word Operation
19.8
Write Buffer Programming Command Sequence
Write Buffer Programming Sequence allows for faster programming as compared to the standard Program Command Sequence. See the Write Buffer Programming Operation section for the program command sequence.
Table 19.11
Sequence Unlock Command 1 Unlock Command 2 Write Buffer Load Specify the Number of Program Locations Load 1st data word Load next data word ... Load last data word Write Buffer Program Confirm Device goes busy Status monitoring through DQ pins (Perform Data Bar Polling on the Last Loaded Address)
Write Buffer Command Sequence
Address 555 2AA Data 00AA 0055 0025h Word Count Number of locations to program minus 1 Comment Not required in the Unlock Bypass mode Same as above
Sector Address Starting Address
Starting Address Write Buffer Location ... Write Buffer Location Sector Address
All addresses must be within write-bufferProgram Data page boundaries, but do not have to be loaded in any order Program Data Same as above ... Same as above
Program Data Same as above 0029h This command must follow the last write buffer location loaded, or the operation will ABORT
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Write "Write to Buffer" command and Sector Address
Write number of addresses to program minus 1 and Sector Address
Part of "Write to Buffer" Command Sequence
Write first address/data
Yes
WC = 0 ? No Abort Write to Buffer Operation? No Write next address/data pair Yes Write to buffer ABORTED. Must write "Write-to-buffer Abort Reset" command sequence to return to read mode. Write to a different sector address
WC = WC - 1
Write program buffer to flash sector address
Read DQ15 - DQ0 at Last Loaded Address
DQ7 = Data? No No DQ1 = 1? Yes DQ5 = 1? Yes Read DQ15 - DQ0 with address = Last Loaded Address No
Yes
DQ7 = Data? No FAIL or ABORT
Yes
PASS
Figure 19.3
Write Buffer Programming Operation
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19.8.1
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to primarily program to the device faster than using the standard word program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. During the unlock bypass mode, only the Unlock Bypass Program command is valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data 90h. The second cycle need only contain the data 00h. The device then returns to the read mode.
19.9
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. The Command Definitions table shows the address and data requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7 or DQ6/DQ2. Refer to the Write Operation Status section for information on these status bits. Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. Figure 20.4 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations table in the AC Characteristics section for parameters and timing diagrams.
19.10 Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. The Command Definitions table shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of no less than 50 s occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than
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tSEA. Any sector erase address and command following the exceeded time-out may or may not be accepted. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to the read mode. The system can monitor DQ3 to determine if the sector erase timer has timed out (See DQ3: Sector Erase Timer.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by reading DQ7 or DQ6/DQ2. Refer to the Write Operation Status section for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. Figure 20.4 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations table in the Erase/Program Operations section for parameters and timing diagrams.
19.10.1 Accelerated Sector Erase
Under certain conditions, the device can erase sectors in parallel. This method of erasing sectors is faster than the standard sector erase command sequence. Table 19.6lists the sectors. The accelerated sector erase function must not be used more than 100 times per sector. In addition, accelerated sector erase should be performed at room temperature 30C (+/-) 5C. Use the following procedure to perform accelerated sector erase: 1. 2. 3. 4. 5. 6. 7. Unlock all sectors in a sector to be erased using the sector lock/unlock command sequence. All sectors that remain locked will not be erased. Apply 9 V to the ACC input. This voltage must be applied at least 1 s before executing step 3. Write 80h to any address within a sector to be erased. Write 30h to any address within a sector to be erased. Monitor status bits DQ2/DQ6 or DQ7 to determine when erasure is complete, just as in the standard erase operation. See the Write Operation Status section for further details. Lower ACC from 9 V to VCC. Relock sectors as required.
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20 Erase Suspend/Erase Resume Commands
Notes:
1.See the Command Definitions table for erase command sequence. 2.See the section on DQ3 for information on the sector erase timer.
Figure 20.4
Erase Operation
The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the minimum tSEA time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of tESL (Erase Suspend Latency) to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the device enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device erase suspends all sectors selected for erasure.) Reading at any address within erasesuspended sectors produces status information on DQ7-DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See Write Operation Status for information on these status bits. After an erase-suspended program operation is complete, the device returns to the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See Write Operation Status for more information. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. See Write Buffer Programming Operation and Autoselect Command Sequence for details. To resume the sector erase operation, the system must write the Erase Resume command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing.
20.1
Program Suspend/Program Resume Commands
The Program Suspend command allows the system to interrupt a embedded programming operation or a Write to Buffer programming operation so that data can read from any non-suspended sector. When the Program Suspend command is written during a programming process, the device halts the programming operation within tPSL (Program Suspend Latency) and updates the status bits. Addresses are don't-cares when writing the Program Suspend command. After the programming operation has been suspended, the system can read array data from any non-suspended sector. The Program Suspend command may also be issued during a programming operation while an erase is suspended. In this case, data may be read from any addresses not in Erase Suspend or Program Suspend. If a read is needed from the SecSi Sector area (One Time Program area), then user must use the proper command sequences to enter and exit this region. The system may also write the autoselect command sequence when the device is in Program Suspend mode. The device allows reading autoselect codes in the suspended sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to Program Suspend mode, and is ready for another valid operation. See Autoselect Command Sequence for more information.
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After the Program Resume command is written, the device reverts to programming. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See Write Operation Status for more information. The system must write the Program Resume command (address bits are don't care) to exit the Program Suspend mode and continue the programming operation. Further writes of the Program Resume command are ignored. Another Program Suspend command can be written after the device has resume programming.
20.2 Volatile Sector Protection Command Set
The Volatile Sector Protection Command Set permits the user to set the Dynamic Protection Bit (DYB), clear the Dynamic Protection Bit (DYB), and read the logic state of the Dynamic Protection Bit (DYB). The Volatile Sector Protection Command Set Entry command sequence must be issued prior to any of the commands listed following to enable proper command execution. Note that issuing the Volatile Sector Protection Command Set Entry command disables reads and writes for the device with the command. DYB Set Command DYB Clear Command DYB Status Read Command The DYB Set/Clear command is used to set or clear a DYB for a given sector. The address bits are issued at the same time as the code 00h or 01h on DQ7-DQ0. All other DQ data bus pins are ignored during the data write cycle. The DYBs are modifiable at any time, regardless of the state of the PPB or PPB Lock Bit. The DYBs are cleared (erased to `1') at power-up or hardware reset and are thus in an unprotected state. The programming state of the DYB for a given sector can be verified by writing a DYB Status Read Command to the device. The Volatile Sector Protection Command Set Exit command must be issued after the execution of the commands listed previously to reset the device to read mode. Otherwise the device will hang. Note that issuing the Volatile Sector Protection Command Set Exit command re-enables reads and writes for the device.
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21 Command Definitions
Command Sequence (Note 1) First Addr Data RA RD XXX F0 555 AA 555 AA 555 AA 555 AA 555 AA SA 29 555 AA 555 AA 555 AA XXX B0 XXX 30 555 AA 555 AA 555 AA XX A0 XX 90 555 XX XX SA XX AA A0 A0 RD(0) 90 Second Addr Data Bus Cycles (Notes 1-6) Third Fourth Addr Data Addr Data Cycles Fifth Addr Data Sixth Addr Data
Asynchronous Read (7) 1 Reset (8) 1 Manufacturer ID 4 Autoselect Device ID (10) 6 (9) Indicator Bits 4 Program 4 Write to Buffer (18) 6 Program Buffer to Flash 1 Write to Buffer Abort Reset (22) 3 Chip Erase 6 Sector Erase 6 Erase Suspend (15) 1 Erase Resume (15) 1 Set Configuration Register (16) 4 Read Configuration Register (17) 4 Unlock Bypass Entry (21) 3 Unlock Bypass Unlock Bypass Program (12, 13) 2 Mode Unlock Bypass Reset 2 Volatile Sector Protection Command Set Definitions Volatile Sector Protection 3 Command Set Entry DYB Set 2 DYB DYB Clear 2 DYB Status Read 1 Volatile Sector Protection 2 Command Set Exit
2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA
55 55 55 55 55 55 55 55
555 555 555 555 SA 555 555 555
90 90 90 A0 25 F0 80 80
X00 X01 X03 PA PA
0001 (11) (11) Data WC
X0E
(10)
X0F
(10)
PA
PD
WBL
PD
555 555
AA AA
2AA 2AA
55 55
555 SA
10 30
2AA 2AA 2AA PA XXX 2AA SA SA XX
55 55 55 PD 00 55 00 01 00
555 555 555
D0 C6 20
X00 or X01 X00 or X01
CR CR
555
E0
Legend: X = Don't care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the rising edge of the AVD# pulse or active edge of CLK which ever comes first. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A24-A14 for the RS512N uniquely select any sector. CR = Configuration Register data bits D15-D0. WBL = Write Buffer Location. Address must be within the same write buffer page as PA. WC = Word Count. Number of write buffer locations to load minus 1.
Notes:
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. See Table 18.1 for description of bus operations. All values are in hexadecimal. Except for the following, all bus cycles are write cycle: read cycle, fourth through sixth cycles of the Autoselect commands, fourth cycle of the configuration register verify command, and any cycle reading at RD(0) and RD(1). Data bits DQ15-DQ8 are don't care in command sequences, except for RD, PD, and WD. Unless otherwise noted, address bits Amax-A12 are don't cares. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset command to return the device to reading array data. No unlock or command cycles required when device is reading array data. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase Suspend) when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status information) or performing sector lock/unlock. The fourth cycle of the autoselect command sequence is a read cycle. See the Autoselect Command Sequence section. 512 Mb: 0Eh = 29h and 0Fh = 01h. See the Autoselect Command Sequence section. The Unlock Bypass command sequence is required prior to this command sequence. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. The Erase Resume command is valid only during the Erase Suspend mode See the Set Configuration Register Command Sequence section. See the Read Configuration Register Command Sequence section which further provides information on Reset Command to Configure the Configuration Register. The total number of cycles in the command sequence is determined by the number of words written to the write buffer. The maximum number of cycles in the command sequence is 37. ACC must be at VHH during the entire operation of this command Command sequence resets device for next command after write-to-buffer operation. Entry commands are needed to enter a specific mode to enable instructions only available within that mode. Write Buffer Programming can be initiated after Unlock Bypass Entry.
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22 Write Operation Status
The device provides several bits to determine the status of a program or erase operation: DQ1, DQ2, DQ3, DQ5, DQ6, and DQ7. Table 22.13 and the following subsections describe the function of these bits. DQ7 and DQ6 each offers a method for determining whether a program or erase operation is complete or in progress.
22.1
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. Note that the Data# Polling is valid only for the last word being programmed in the write-buffer-page during Write Buffer Programming. Reading Data# Polling status on any word other than the last word to be programmed in the write-buffer-page will return false status information. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately tPSP, then the device returns to the read mode. During the Embedded Erase algorithm, Data# Polling produces a 0 on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a 1 on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately tASP, then the device returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ6-DQ0 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ6-DQ0 may be still invalid. Valid data on DQ7-D00 will appear on successive read cycles. Table 22.13 shows the outputs for Data# Polling on DQ7. Figure 22.5 shows the Data# Polling algorithm. Figure 25.13 in the AC Characteristics section shows the Data# Polling timing diagram.
Notes:
1. 2. VA = Valid adntsbdress for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5.
Figure 22.5
Data# Polling Algorithm
22.2 DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address in the device, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out.
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During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately tASP (All Sectors Protected toggle time), then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erasesuspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately tPSP after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. See the following for additional information: Figure 22.6, Figure 25.14 (toggle bit timing diagram), and Table 22.12. Toggle Bit I on DQ6 requires either OE# or CE# to be deasserted and reasserted to show the change in state.
Note: The system should recheck the toggle bit even if DQ5 = 1 because the toggle bit may stop toggling as DQ5 changes
to 1. See the subsections on DQ6 and DQ2 for more information.
Figure 22.6
Toggle Bit Algorithm
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DQ2: Toggle Bit II
The Toggle Bit II on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erasesuspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. But DQ2 by itself cannot distinguish whether the sector is actively erasing or is erasesuspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 22.12 to compare outputs for DQ2 and DQ6. See Figure 22.6 and Figure 25.14 for additional information.
22.3
Reading Toggle Bits DQ6/DQ2
Whenever the system initially begins reading toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7-DQ0 on the following read cycle. (See Figure 22.6) However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation.
22.4 DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a 1, indicating that the program or erase cycle was not successfully completed. The device may output a 1 on DQ5 if the system tries to program a 1 to a location that was previously programmed to 0 Only an erase operation can change a 0 back to a 1. Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a 1. Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if the device was previously in the erase-suspend-program mode).
22.5 DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a 0 to a 1. If
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the time between additional sector erase commands from the system can be assumed to be less than tSEA, the system need not monitor DQ3. See also the Sector Erase Command Sequence section. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is 1, the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is 00 the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 22.13 shows the status of DQ3 relative to the other status bits.
22.6 DQ1: Write to Buffer Abort
DQ1 indicates whether a Write to Buffer operation was aborted. Under these conditions DQ1 produces a `1'. The system must issue the Write to Buffer Abort Reset command sequence to return the device to reading array data. See the Write Buffer Programming Operation section for more details.
3. 4. 5. DQ1 indicates the Write to Buffer ABORT status during Write Buffer Programming operations. The data-bar polling algorithm should be used for Write Buffer Programming operations. Note that DQ7# during Write Buffer Programming indicates the data-bar for DQ7 data for the LAST LOADED WRITE-BUFFER ADDRESS location. Minimum DC input voltage on pin ACC is -0.5V. During voltage transitions, ACC may overshoot
ACC (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 V to +9.5 V
6.
20 ns +0.8 V -0.5 V -2.0 V 20 ns
20 ns
Table 22.1
Maximum Negative Overshoot Waveform
20 ns VCC +2.0 V VCC +0.5 V 1.0 V 20 ns 20 ns
Figure 22.7
Maximum Positive Overshoot Waveform
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23 DC Characteristics
23.1 CMOS Compatible
Parameter ILI ILO Description Input Load Current Output Leakage Current Test Conditions (Note 1) VIN = VSS to VCC, VCC = VCCmax VOUT = VSS to VCC, VCC = VCCmax CE# = VIL, OE# = VIH, WE# = VIH, burst length = 8 80 MHz 66 MHz 54 MHz 80 MHz 66 MHz 54 MHz 80 MHz 66 MHz 54 MHz 80 MHz 66 MHz 54 MHz 10 MHz ICC1 VCC Active Asynchronous Read Current (Note 2) CE# = VIL, OE# = VIH, WE# = VIH CE# = VIL, OE# = VIH, ACC = VIH CE# = RESET# = VCC 0.2 V RESET# = VIL, CLK = VIL CE# = VIL, OE# = VIH CE# = VIL, OE# = VIH, VACC = 9.5 V VCC VACC -0.5 VCC - 0.4 IOL = 100 A, VCC = VCC min IOH = -100 A, VCC = VCC min VCC - 0.1 8.5 1.0 9.5 1.4 5 MHz 1 MHz ICC2 VCC Active Write Current (Note 3) VCC Standby Current (Note 6) VCC Reset Current VCC Sleep Current Accelerated Program Current (Note 5) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Voltage for Accelerated Program Low VCC Lock-out Voltage VCC VACC VCC VACC 30 28 27 32 30 28 34 32 29 38 35 22 27 13 3 <35 20 20 10 70 20 <30 <15 Min Typ (Note 7) Max 1 1 66 60 54 60 54 48 54 48 42 48 42 36 36 18 4 <50 30 40 15 150 40 <40 <20 0.4 VCC + 0.4 0.1 V V V V mA mA mA mA A A A A A mA mA V mA mA mA mA Unit A A
CE# = VIL, OE# = VIH, WE# = VIH, burst length = 16 ICCB VCC Active burst Read Current CE# = VIL, OE# = VIH, WE# = VIH, burst length = 32
CE# = VIL, OE# = VIH, WE# = VIH, burst length = Continuous
ICC3 ICC4 ICC6 IACC VIL VIH VOL VOH VHH VLKO
Notes:
1. 2. 3. 4. 5. 6. 7. Maximum ICC specifications are tested with VCC = VCC max. The ICC current listed is typically less than 2-3 mA/MHz, with OE# at VIH. ICC active while Embedded Erase or Embedded Program is in progress. Device enters automatic sleep mode when addresses are stable for tACC + 20 ns. Typical sleep mode current is equal to ICC3. Total current during accelerated programming is the sum of VACC and VCC currents. UIH = VCC 0.2 V and VIL > -.1 V Typical test conditions of room temperature and 1.8 V VCC.
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24 Test Conditions
Device Under Test CL
Figure 24.1 Table 24.1
Test Condition
Test Setup
Test Specifications
All Speed Options
30 2.5 0.0-VCC VCC/2 VCC/2
Unit
pF ns V V V
Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels
Figure 24.2
Waveform Steady
Input Waveforms and Measurement Levels
Inputs Outputs
Changing from H to L
Changing from L to H
Don't Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
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25 AC Characteristics
25.1 VCC Power-up
Parameter tVCS Description VCC Setup Time Test Setup Min Speed 1 Unit ms
Notes:
1. 2. VCC >= VIO - 100mV and VCC ramp rate is > 1V / 100s VCC ramp rate <1V / 100s, a Hardware Reset will be required.
tVCS
VCC
RESET#
Figure 25.1
VCC Power-up Diagram
25.2 CLK Characterization
Parameter
fCLK tCLK tCH tCL tCR tCF
Description
CLK Frequency CLK Period CLK High Time CLK Low Time CLK Rise Time CLK Fall Time Max Min Min
80 MHz
80 12.5 3.5
66 MHz
66 15.1 6.1
54 MHz
54 18.5 7.40
Unit
MHz ns ns
Max
2
3
3
ns
tCLK tCF tCH tCR tCL
CLK
Figure 25.2
CLK Characterization
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25.3
Synchronous/Burst Read
Parameter JEDEC Standard tIACC tBACC tACS tACH tBDH tCR tOE tCEZ tOEZ tCES tRDYS tRACC tAAS tAAH tCAS tAVC tAVD Latency Burst Access Time Valid Clock to Output Delay Address Setup Time to CLK (Note 1) Address Hold Time from CLK (Note 1) Data Hold Time from Next Clock Cycle Chip Enable to RDY Valid Output Enable to Output Valid Chip Enable to High Z (Note 2) Output Enable to High Z (Note 2) CE# Setup Time to CLK RDY Setup Time to CLK Ready Access Time from CLK Address Setup Time to AVD# (Note 1) Address Hold Time to AVD# (Note 1) CE# Setup Time to AVD# AVD# Low to CLK AVD# Pulse Description Max Max Min Min Min Max Max Max Max Min Min Max Min Min Min Min Min 9.1 4 2 4 9.1 9.1 10 10 4 4 9.1 4 2 0 4 8 80 MHz 66 MHz 148 11.2 4 2 4 11.2 11.2 10 10 4 4 11.2 4 2 0 4 8 13.5 5 3 5 13.5 13.5 10 10 4 5 13.5 5 3 0 4 8 54 MHz Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes:
1. 2. Addresses are latched on the first rising edge of CLK. Not 100% tested.
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10 cycles for initial access shown.
tCES CE# 1 CLK tAVC AVD# tACS Addresses
Aa
18.5 ns typ. (54 MHz)
tCEZ 11 12
2
3
9
10
tAVD
tACH Data (n) tIACC OE# tOE RDY (n)
Hi-Z Da Da + 1
tBACC
Hi-Z Da + 2 Da + n
tBDH tRACC
tOEZ
Hi-Z
tCR
tRDYS
Hi-Z Da Da + 1 Da + 2 Da + n
Data (n + 1)
RDY (n + 1)
Hi-Z
Hi-Z
Data (n + 2)
Da Da + 1 Da + 1 Da + n
Hi-Z
RDY (n + 2)
Hi-Z
Hi-Z
Data (n + 3)
Da Da Da Da + n
Hi-Z
RDY (n + 3)
Hi-Z
Hi-Z
Notes:
1. 2. 3. 4. Figure shows total number of wait states set to ten cycles. The total number of wait states can be programmed from three cycles to thirteen cycles. If any burst address occurs at address + 1, address + 2, ..., or address + 7, additional clock delay cycles are inserted, and are indicated by RDY. The device is in synchronous mode. In order for the device to operate at 80Mhz/66Mhz/54Mhz, there is an additional wait state latency of 2/1/0 accordingly, every 4 clock cycles with the first data being read.
Figure 25.3
CLK Synchronous Burst Mode Read
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tCES CE# 1 CLK tAVC AVD# tACS Addresses
Ac
12 cycles for initial access shown.
2
3
9
10
11
12
tAVD
tACH Data tIACC OE# tCR RDY
Hi-Z DC DD
tBACC
DE
DF
D8
DB
tBDH
tOE
tRACC
tRACC
tRDYS
Notes:
1. 2. 3. 4. Figure shows total number of wait states set to twelve cycles. The total number of wait states can be programmed from three cycles to thirteen cycles. Clock is set for active rising edge. If any burst address occurs at address + 1, address + 2, ..., or address + 7, additional clock delay cycles are inserted, and are indicated by RDY. The device is in synchronous mode with wrap around. In order for the device to operate at 80Mhz/66Mhz/54Mhz, there is an additional wait state latency of 2/1/0 accordingly, every 4 clock cycles with the first data being read. D8-DF in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting address in figure is the 4th address in range (O-F).
Figure 25.4
tCES CE# 1 CLK tAVC AVD# tACS Addresses
AC
8-word Linear Burst with Wrap Around
12 cycles for initial access shown.
2
3
9
10
11
12
tAVD
tACH Data tIACC OE# tCR RDY
Hi-Z DC DD
tBACC
DE
DF
D10
D13
tBDH
tOE
tRACC
tRACC
tRDYS
Notes:
1. 2. 3. 4. Figure shows total number of wait states set to twelve cycles. The total number of wait states can be programmed from three cycles to thirteen cycles. Clock is set for active rising edge. If any burst address occurs at address + 1, address + 2, ..., or address + 7, additional clock delay cycles are inserted, and are indicated by RDY. In order for the device to operate at 80Mhz/66Mhz/54Mhz, there is an additional wait state latency of 2/1/0 accordingly, every 4 clock cycles with the first data being read. DC-D13 in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting address in figure is the 4th address in range (C-13).
Figure 25.5 8-word Linear Burst without Wrap Around
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tCES CE# 1 CLK tAVC AVD# tACS Addresses
Aa
12 wait cycles for initial access shown.
tCEZ 11
2
3
4
10
tAVD
tACH Data tIACC OE# tCR RDY
Hi-Z Da Da+1
tBACC
Hi-Z Da+2 Da+3 Da + n
tBDH tRACC tOE
tOEZ
Hi-Z
tRDYS
Notes:
1. 2. Figure assumes eleven wait states for initial access and synchronous read. The Set Configuration Register command sequence has been written with A18=0; device will output RDY one cycle before valid data.
Figure 25.6
Burst with RDY Set One Cycle Before Data
25.4 Asynchronous Mode Read @ VIO = 1.8 V
Parameter JEDEC Standard tCE tACC tAVDP tAAVDS tAAVDH tOE tOEH tOEZ tCAS Description Access Time from CE# Low Asynchronous Access Time (Note 1) AVD# Low Time Address Setup Time to Rising Edge of AVD# Address Hold Time from Rising Edge of AVD# Output Enable to Output Valid Output Enable Hold Time Read Data# Polling Max Max Min Min Min Max Min Min Max Min 8 4 2 9.1 0 10 10 0 80 MHz 66 MHz 148 143 8 4 2 11.2 0 10 10 0 10 5 3 13.5 0 10 10 0 54 MHz Unit ns ns ns ns ns ns ns ns ns ns
Output Enable to High Z (Note 2) CE# Setup Time to AVD#
Notes:
1. 2. Asynchronous Access Time is from the last of either stable addresses or the falling edge of AVD#. Not 100% tested.
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25.5 Timing Diagrams
CE# tOE tOEH WE# Data tACC Addresses tCAS AVD# tAVDP tAAVDS
Note: RA = Read Address, RD = Read Data.
OE#
tCE Valid RD
tOEZ
RA tAAVDH
Figure 25.7
CE#
Asynchronous Mode Read with Latched Addresses
OE# tOEH WE# Data tACC Addresses RA tCE
tOE
tOEZ Valid RD
AVD#
Note: RA = Read Address, RD = Read Data.
Figure 25.8
Asynchronous Mode Read
25.6 Hardware Reset (RESET#)
Parameter JEDEC Std tRP tRH tRPD RESET# Pulse Width Reset High Time Before Read to Read Mode RESET# Low to Standby Mode Description Min Min Min All Speeds 30 300 20 Unit s s s
Note: Not 100% tested.
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CE#, OE# tRH RESET# tRP
Reset Timings
Figure 25.9
Reset Timings
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25.7 Erase/Program Operations
Parameter JEDEC tAVAV tAVWL Standard tWC tAS Description Write Cycle Time (Note 1) Address Setup Time (Notes 2, 3) Synchronous Asynchronous Synchronous Asynchronous Min Min 80 MHz 66 MHz 70 5 0 2 0 8 20 0 0 0 0 0 2 0 8 20 0 0 0 0 30 20 0 20 0 500 1 50 5 5 2 2 5 2 2 5 3 50 20 20 100 1 3 3 25 0 0 3 0 8 25 0 0 0 0 54 MHz Unit ns ns
tWLAX
tAH tAVDP
Address Hold Time (Notes 2, 3) AVD# Low Time Data Setup Time Data Hold Time Read Recovery Time Before Write CE# Setup Time to AVD# CE# Hold Time Write Pulse Width Write Pulse Width Highs
Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Max Max Max Max Typ Typ
ns ns ns ns ns ns ns ns ns ns ns s s ns ns ns ns ns ns ns s s s s s
tDVWH tWHDX tGHWL
tDS tDH tGHWL tCAS
tWHEH tWLWH tWHWL
tCH tWP tWPH tSR/W tVID tVIDS tVCS
Latency Between Read and Write Operations VACC Rise and Fall Time VACC Setup Time (During Accelerated Programming) VCC Setup Time CE# Setup Time to WE# AVD# Setup Time to WE# AVD# Hold Time to WE# AVD# Setup Time to CLK AVD# Hold Time to CLK Clock Setup Time to WE# Noise Pulse Margin on WE# Sector Erase Accept Time-out Erase Suspend Latency Program Suspend Latency Toggle Time During Sector Protection Toggle Time During Programming Within a Protected Sector
tELWL
tCS tAVSW tAVHW tAVSC tAVHC tCSW tWEP tSEA tESL tPSL tASP tPSP
Notes:
1. 2. 3. 4. Not 100% tested. Asynchronous read mode allows Asynchronous program operation only. Synchronous read mode allows both Asynchronous and Synchronous program operation. In asynchronous program operation timing, addresses are latched on the falling edge of WE#. In synchronous program operation timing, addresses are latched on the rising edge of CLK. See the Erase and Programming Performance section for more information. Does not include the preprogramming time.
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Data
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Program Command Sequence (last two cycles)
Read Status Data
VIH
CLK
VIL
tAVSW tAVDP tAVHW
AVD# tAS tAH Addresses 555h PA VA
In Progress
VA
Data tCAS CE#
A0h tDS tDH
PD
Complete
OE# tWP WE#
tCH
tWHWH1 tCS tWC tVCS VCC tWPH
Notes:
1. 2. 3. 4. 5. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. In progress and complete refer to status of program operation. Amax-A14 are don't care during command sequence unlock cycles. CLK can be either VIL or VIH. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Configuration Register.
Figure 25.10
Asynchronous Program Operation Timings: WE# Latched Addresses
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Program Command Sequence (last two cycles) tAVCH CLK tAS tAH tAVSC AVD# tAVDP Addresses 555h PA VA
Read Status Data
VA
In Progress
Data tCAS CE#
A0h
PD tDS tDH
Complete
OE#
tCSW tWP
tCH
WE# tWHWH1 tWPH tWC
tVCS VCC
Notes:
1. 2. 3. 4. 5. 6. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. In progress and complete refer to status of program operation. Amax9-A14 are don't care during command sequence unlock cycles. Addresses are latched on the rising edge of CLK. Either CE# or AVD# is required to go from low to high in between programming command sequences. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register. The Configuration Register must be set to the Synchronous Read Mode.
Figure 25.11
CE#
Synchronous Program Operation Timings: CLK Latched Addresses
AVD# WE# Addresses Data Don't Care A0h
PA Don't Care PD Don't Care
OE# ACC
VID
tVIDS tVID
VIL or VIH
Note: Use setup and hold times from conventional program operation.
Figure 25.12
Accelerated Unlock Bypass Programming Timing
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Data
Sheet
AVD# tCE CE# tCH OE# tOEH WE# tACC Addresses VA VA
High Z
tCEZ
tOE
tOEZ
High Z
Data
Status Data
Status Data
Notes:
1. 2. Status reads in figure are shown as asynchronous. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is completeData# Polling will output true data.
Figure 25.13
Data# Polling Timings (During Embedded Algorithm)
AVD# tCE CE# tCH OE# tOEH WE# tACC Addresses VA VA
High Z
tCEZ
tOE
tOEZ
Data
High Z
Status Data
Status Data
Notes:
1. 2. Status reads in figure are shown as asynchronous. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, .
Figure 25.14
Toggle Bit Timings (During Embedded Algorithm)
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Data
Sheet
CE#
CLK
AVD#
Addresses
VA
VA
OE#
tIACC tIACC Status Data Status Data
Data
RDY
Notes:
1. 2. 3. The timings are similar to synchronous read timings. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, . RDY is active with data (D8 = 0 in the Configuration Register). When D8 = 1 in the Configuration Register, RDY is active one clock cycle before data.
Figure 25.15
Enter Embedded Erasing WE#
Synchronous Data Polling Timings/Toggle Bit Timings
Enter Erase Suspend Program Erase Suspend Program
Erase Suspend Erase
Erase Resume Erase Suspend Read Erase Erase Complete
Erase Suspend Read
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to
toggle DQ2 and DQ6.
Figure 25.16
DQ2 vs. DQ6
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Data
Sheet
Address boundary occurs every 512 words, beginning at address 0001FFh: (0002FFh, 0003FFh, etc.) Address 000000h is also a boundary crossing.
C508 CLK Address (hex) AVD# 1FC (stays high)
C509 1FD
C510 1FE
C511 1FF
C511 1FF
C512 200
C513 201
C514 202
C515 203
tRACC RDY(1) tRACC RDY(2)
latency latency
tRACC
tRACC
Data
D508
D509
D510
D511
D512
D513
D514
OE#, CE#
Notes:
1. 2. 3. 4.
(stays low)
RDY active with data (D8 = 0 in the Configuration Register). RDY active one clock cycle before data (D8 = 1 in the Configuration Register). Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. There will be an additional 4/8 wait state latency for 54/80 Mhz respectively.
Figure 25.17
Data
Latency with Boundary Crossing
D0 D1
AVD#
Rising edge of next clock cycle following last wait state triggers next burst data total number of clock cycles following AVD# falling edge
OE# 1 CLK 2 3
4
5
6
7
8
9
10
11
12
13
14
0
1
2
3
4
5
number of clock cycles programmed
Wait State Configuration Register Setup
CR1.0, CR1.0, CR1.0, CR1.0, CR1.0, CR1.0, CR1.0, CR1.0, CR1.0, CR1.0, CR1.0, CR0.13, CR0.13, CR0.13, CR0.13, CR0.13, CR0.13, CR0.13, CR0.13, CR0.13, CR0.13, CR0.13, CR0.12, CR0.12, CR0.12, CR0.12, CR0.12, CR0.12, CR0.12, CR0.12, CR0.12, CR0.12, CR0.12, CR0.11= CR0.11= CR0.11= CR0.11= CR0.11= CR0.11= CR0.11= CR0.11= CR0.11= CR0.11= CR0.11= 1101 1100 1011 1010 1001 1000 0101 0100 0011 0010 0001 13 total 12 total 11 total 10 total 9 total 8 total 7 total 6 total 5 total 4 total 3 total
Note: Figure assumes address D0 is not at an address boundary.
Figure 25.18
Example of Wait States Insertion
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Data
Sheet
Last Cycle in Program or Sector Erase Command Sequence
Read status (at least two cycles) in same bank and/or array data from other bank
Begin another write or program command sequence
tWC
tRC
tRC
tWC
CE#
OE# tOE tOEH WE# tWPH tWP tDS tDH Data
PD/30h RD
tGHWL
tACC
tOEZ tOEH
RD AAh
tSR/W Addresses
PA/SA RA RA 555h
tAS AVD# tAH
Note: Breakpoints in waveforms indicate that system may alternately read the status of the program or erase operation in
the device. The system should read status twice to ensure valid information.
Figure 25.19
Back-to-Back Read/Write Cycle Timings
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26 Erase and Programming Performance
Parameter VCC ACC VCC ACC VCC ACC VCC ACC VCC ACC VCC ACC Typ (Note 1) 2 1 308 262 <40 <24 <9.4 <6 <300 <192 <314.6 <201.4 Max (Note 2) 20 10 616 524 <400 <240 <94 <60 <3000 <1920 <629.2 <402.6 Unit Comments
Sector Erase Time
256 Kword
s Excludes 00h programming prior to erasure (Note 4) s
Chip Erase Time
Word Programming Time
s
Excludes system level overhead (Note 5)
Effective Word Programming Time utilizing Program Write Buffer
s
Total 32-Word BufferProgramming Time
s
Chip Programming Time (Note 3)
s
Excludes system level overhead (Note 5)
Notes:
1. 2. 3. 4. 5. 6. Typical program and erase times assume the following conditions: 25C, 1.8 V VCC, 100,000 cycles typical. Additionally, programming typically assumes a checkerboard pattern. Under worst case conditions of 90C, VCC = 1.65 V, 100,000 cycles. The typical chip programming time is considerably less than the maximum chip programming time listed. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See the Command Definitions table for further information on command definitions. The device has a minimum erase and program cycle endurance of 100,000 cycles.
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CellularRAM
128/64/32 Megabit Burst CellularRAM
Features
Single device supports asynchronous, page, and burst operations VCC Voltages
-- 1.70V-1.95V VCC
Low-Power Consumption
-- -- -- -- -- -- Asynchronous Read < 25mA Intrapage Read < 15mA Initial access, burst Read < 35mA Continuous burst Read < 11mA Standby: 180A Deep power-down < 10A
Random Access Time: 70ns Burst Mode Write Access
-- Continuous burst
Burst Mode Read Access
-- 4, 8, or 16 words, or continuous burst
Low-Power Features
-- Temperature Compensated Refresh (TCR) On-chip sensor control -- Partial Array Refresh (PAR) -- Deep Power-Down (DPD) Mode
Page Mode Read Access
-- Sixteen-word page size -- Interpage Read access: 70ns -- Intrapage Read access: 20ns
General Description
CellularRAMTM products are High-speed, CMOS dynamic random access memories developed for lowpower, portable applications. These devices include an industry standard burst mode Flash interface that dramatically increases Read/Write bandwidth compared with other low-power SRAM or Pseudo SRAM offerings. To operate seamlessly on a burst Flash bus, CellularRAM products incorporate a transparent self-refresh mechanism. The hidden refresh requires no additional support from the system memory controller and has no significant impact on device Read/Write performance. Two user-accessible control registers define device operation. The bus configuration register (BCR) defines how the CellularRAM device interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh configuration register (RCR) is used to control how refresh is performed on the DRAM array. These registers are automatically loaded with default settings during power-up and can be updated anytime during normal operation. Special attention has been focused on standby current consumption during self refresh. CellularRAM products include three mechanisms to minimize standby current. Partial array refresh (PAR) enables the system to limit refresh to only that part of the DRAM array that contains essential data. Temperature compensated refresh (TCR) adjusts the refresh rate to match the device temperature--the refresh rate decreases at lower temperatures to minimize current consumption during standby. Deep power-down (DPD) enables the system to halt the refresh operation altogether when no vital information is stored in the device. The system-configurable refresh mechanisms are accessed through the RCR.
Publication Number S75WS-N-00
Revision A
Amendment 0
Issue Date February 17, 2005
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27 Functional Block Diagram
128M: A[22:0] 64M: A[21:0] 32M: A[20:0] Address Decode Logic Input/ Output MUX and Buffers DQ[7:0]
DRAM MEMORY ARRAY
Refresh Configuration Register (RCR)
DQ[15:8]
Bus Configuration Register (BCR)
CE# WE# OE# CLK ADV# CRE WAIT LB# UB#
Control Logic
Note: Functional block diagrams illustrate simplified device operation. See truth table, ball descriptions, and timing diagrams for detailed information.
Figure 27.1
Functional Block Diagram
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Table 27.1
Symbol 128M: A[22:0] 64M: A[21:0] 32M: A[20:0] Type Input
Signal Descriptions
Description
Address Inputs: Inputs for addresses during Read and Write operations. Addresses are internally latched during Read and Write cycles. The address lines are also used to define the value to be loaded into the BCR or the RCR. Clock: Synchronizes the memory to the system operating frequency during synchronous operations. When configured for synchronous operation, the address is latched on the first rising CLK edge when ADV# is active. CLK is static (High or Low) during asynchronous access Read and Write operations and during Page Read Access operations. Address Valid: Indicates that a valid address is present on the address inputs. Addresses can be latched on the rising edge of ADV# during asynchronous Read and Write operations. ADV# can be held Low during asynchronous Read and Write operations. Configuration Register Enable: When CRE is High, Write operations load the RCR or BCR. Chip Enable: Activates the device when Low. When CE# is High, the device is disabled and goes into standby or deep power-down mode. Output Enable: Enables the output buffers when Low. When OE# is High, the output buffers are disabled. Write Enable: Determines if a given cycle is a Write cycle. If WE# is Low, the cycle is a Write to either a configuration register or to the memory array. Lower Byte Enable. DQ[7:0] Upper Byte Enable. DQ[15:8] Data Inputs/Outputs. Wait: Provides data-valid feedback during burst Read and Write operations. The signal is gated by CE#. Wait is used to arbitrate collisions between refresh and Read/Write operations. Wait is asserted when a burst crosses a row boundary. Wait is also used to mask the delay associated with opening a new internal page. Wait is asserted and should be ignored during asynchronous and page mode operations. Wait is High-Z when CE# is High. Device Power Supply: (1.7V-1.95V) Power supply for device core operation. I/O Power Supply: (1.7V-1.95V) Power supply for input/output buffers. VSS must be connected to ground. VSSQ must be connected to ground.
CLK
Input
ADV# CRE CE# OE# WE# LB# UB# DQ[15:0]
Input Input Input Input Input Input Input Input/ Output
Wait
Output
VCC VCCQ VSS VSSQ
Supply Supply Supply Supply
Note: The CLK and ADV# inputs can be tied to VSS if the device is always operating in asynchronous or page mode. Wait will be asserted but should be ignored during asynchronous and page mode operations.
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Table 27.2
Mode Read Write Standby No Operation Configuration Register DPD
Notes:
1. 2. 3. 4. 5. 6. 7.
Bus Operations--Asynchronous Mode
CE# L L H L L H OE# L X X X H X WE# H L X X L X CRE L L L L H X LB#/ UB# L L X X X X Wait (Note 2) Low-Z Low-Z High-Z Low-Z Low-Z High-Z DQ[15:0] (Note 3) Data-Out Data-In High-Z X High-Z High-Z 7 Notes 4 4 5, 6 4, 6
Power Active Active Standby Idle Active Deep Power-down
Clk (Note 1) ADV# X X X X X X L L X X L X
CLK may be High or Low, but must be static during synchronous Read, synchronous Write, burst suspend, and DPD modes; and to achieve standby power during standby and active modes. The Wait polarity is configured through the bus configuration register (BCR[10]). When LB# and UB# are in select mode (Low), DQ[15:0] are affected. When only LB# is in select mode, DQ[7:0] are affected. When only UB# is in the select mode, DQ[15:8] are affected. The device will consume active power in this mode whenever addresses are changed. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence. VIN = VCCQ or 0V; all device balls must be static (unswitched) to achieve standby current. DPD is maintained until RCR is reconfigured.
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Table 27.3
Mode Async Read Async Write Standby No Operation Initial Burst Read Initial Burst Write Burst Continue Burst Suspend Configuration Register DPD
Notes:
1. 2. 3. 4. 5. 6. 7. 8.
Bus Operations--Burst Mode
CE# L L H L L L L L L H OE# L X X X X H X H H X WE# H L X X H L X X L X CRE L L L L L L L L H X LB#/ UB# L L X X L X X X X X Wait (Note 2) Low-Z Low-Z High-Z Low-Z Low-Z Low-Z Low-Z Low-Z Low-Z High-Z DQ[15:0] (Note 3) Data-Out Data-In High-Z X Data-Out Data-In Data-In or Data-Out High-Z High-Z High-Z Notes 4 4 5, 6 4, 6 4, 8 4, 8 4, 8 4, 8 8 7
Power Active Active Standby Idle Active Active Active Active Active Deep Power-Down
CLK (Note 1) ADV# X X X X L L X X L L H X X L X X
CLK may be High or Low, but must be static during asynchronous Read, synchronous Write, burst suspend, and DPD modes; and to achieve standby power during standby and active modes. The Wait polarity is configured through the bus configuration register (BCR[10]). When LB# and UB# are in select mode (Low), DQ[15:0] are affected. When only LB# is in select mode, DQ[7:0] are affected. When only UB# is in the select mode, DQ[15:8] are affected. The device will consume active power in this mode whenever addresses are changed. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence. VIN = VCCQ or 0V; all device balls must be static (unswitched) to achieve standby current. DPD is maintained until RCR is reconfigured. Burst mode operation is initialized through the bus configuration register (BCR[15]).
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28 Functional Description
The CellularRAM bus interface supports both asynchronous and burst mode transfers. Page mode accesses are also included as a bandwidth-enhancing extension to the asynchronous Read protocol.
28.1
Power-Up Initialization
CellularRAM products include an on-chip voltage sensor used to launch the power-up initialization process. Initialization will configure the BCR and the RCR with their default settings (see Table 31.1 and Table 31.5). VCC and VCCQ must be applied simultaneously. When they reach a stable level at or above 1.7V, the device will require 150 s to complete its self-initialization process. During the initialization period, CE# should remain High. When initialization is complete, the device is Ready for normal operation.
tPU > 150 s Device Initialization
VCCQ
VCC
VCC = 1.7 V
Device ready for normal operation
Figure 28.2
Power-Up Initialization Timing
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29 Bus Operating Modes
CellularRAM products incorporate a burst mode interface found on Flash products targeting lowpower, wireless applications. This bus interface supports asynchronous, page mode, and burst mode Read and Write transfers. The specific interface supported is defined by the value loaded into the BCR. Page mode is controlled by the refresh configuration register (RCR[7]).
29.1
Asynchronous Mode
CellularRAM products power up in the asynchronous operating mode. This mode uses the industry standard SRAM control bus (CE#, OE#, WE#, LB#/ UB#). Read operations (Figure 29.1) are initiated by bringing CE#, OE#, and LB#/UB# Low while keeping WE# High. Valid data will be driven out of the I/Os after the specified access time has elapsed. Write operations (Figure 29.2) occur when CE#, WE#, and LB#/ UB# are driven Low. During asynchronous Write operations, the OE# level is a don't care, and WE# will override OE#. The data to be written is latched on the rising edge of CE#, WE#, or LB#/UB# (whichever occurs first). Asynchronous operations (page mode disabled) can either use the ADV input to latch the address, or ADV can be driven Low during the entire Read/Write operation. During asynchronous operation, the CLK input must be held static (High or Low, no transitions). Wait will be driven while the device is enabled and its state should be ignored.
CE#
OE# WE# ADDRESS Address Valid
DATA
Data Valid
LB#/UB#
tRC = READ Cycle Time Don't Care
Note: ADV must remain Low for page mode operation.
Figure 29.1
Read Operation (ADV# Low)
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CE#
OE#
WE#
ADDRESS
Address Valid
DATA
Data Valid
LB#/UB#
tWC = WRITE Cycle Time Don't Care
Figure 29.2
Write Operation (ADV# Low)
29.2 Page Mode Read Operation
Page mode is a performance-enhancing extension to the legacy asynchronous Read operation. In page mode-capable products, an initial asynchronous Read access is performed, then adjacent addresses can be Read quickly by simply changing the low-order address. Addresses A[3:0] are used to determine the members of the 16-address CellularRAM page. Addresses A[4] and higher must remain fixed during the entire page mode access. Figure 29.3 shows the timing for a page mode access. Page mode takes advantage of the fact that adjacent addresses can be Read in a shorter period of time than random addresses. Write operations do not include comparable page mode functionality. During asynchronous page mode operation, the CLK input must be held Low. CE# must be driven High upon completion of a page mode access. Wait will be driven while the device is enabled and its state should be ignored. Page mode is enabled by setting RCR[7] to High. Write operations do not include comparable page mode functionality. ADV must be driven Low during all page mode Read accesses.
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CE#
OE# WE# ADDRESS ADD[0] ADD[1] ADD[2] ADD[3]
tAA DATA
tAPA D[0]
tAPA D[1]
tAPA D[2] D[3]
LB#/UB#
Don't Care
Figure 29.3
Page Mode Read Operation (ADV# Low)
29.3 Burst Mode Operation
Burst mode operations enable High-speed synchronous Read and Write operations. Burst operations consist of a multi-clock sequence that must be performed in an ordered fashion. After CE# goes Low, the address to access is latched on the rising edge of the next clock that ADV# is Low. During this first clock rising edge, WE# indicates whether the operation is going to be a Read (WE# = High, Figure 29.4) or Write (WE# = Low, Figure 29.5). The size of a burst can be specified in the BCR either as a fixed length or continuous. Fixed-length bursts consist of four, eight, or sixteen words. Continuous bursts have the ability to start at a specified address and burst through the entire memory. The latency count stored in the BCR defines the number of clock cycles that elapse before the initial data value is transferred between the processor and CellularRAM device. The Wait output asserts as soon as a burst is initiated, and de-asserts to indicate when data is to be transferred into (or out of) the memory. Wait will again be asserted if the burst crosses a row boundary. Once the CellularRAM device has restored the previous row's data and accessed the next row, Wait will be deasserted and the burst can continue (see Figure 34.9). To access other devices on the same bus without the timing penalty of the initial latency for a new burst, burst mode can be suspended. Bursts are suspended by stopping CLK. CLK can be stopped High or Low. If another device will use the data bus while the burst is suspended, OE# should be taken High to disable the CellularRAM outputs; otherwise, OE# can remain Low. Note that the Wait output will continue to be active, and as a result no other devices should directly share the Wait connection to the controller. To continue the burst sequence, OE# is taken Low, then CLK is restarted after valid data is available on the bus. See How Extended Timings Impact CellularRAMTM Operation for restrictions on the maximum CE# Low time during burst operations. If a burst suspension will cause CE# to remain Low for longer than tCEM, CE# should be taken High and the burst restarted with a new CE# Low/ADV# low cycle.
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CLK A[22:0] ADV# Address Valid
Latency Code 2 (3 clocks), variable CE# OE# WE# WAIT DQ[15:0] LB#/UB# D[0] D[1] D[2] D[3]
READ Burst Identified (WE# = HIGH)
Legend:
Don't care
Undefined
Note: Non-default BCR settings: Variable latency; latency code two (three clocks); Wait active Low; Wait asserted during delay.
Figure 29.4
Burst Mode Read (4-word burst)
CLK A[22:0] ADV# Address Valid
Latency Code 2 (3 clocks), variable CE# OE# WE# WAIT DQ[15:0] LB#/UB# D[0] D[1] D[2] D[3]
WRITE Burst Identified (WE# = LOW)
Legend:
Don't care
Note: Non-default BCR settings: Variable latency; latency code two (three clocks); Wait active Low; Wait asserted during delay.
Figure 29.5
Burst Mode Write (4-word burst)
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29.4 Mixed-Mode Operation
The device can support a combination of synchronous Read and asynchronous Write operations when the BCR is configured for synchronous operation. The asynchronous Write operation requires that the clock (CLK) remain static (High or Low) during the entire sequence. The ADV# signal can be used to latch the target address, or it can remain Low during the entire Write operation. CE# can remain Low when transitioning between mixed-mode operations with fixed latency enabled. Note that the tCKA period is the same as a Read or Write cycle. This time is required to ensure adequate refresh. Mixed-mode operation facilitates a seamless interface to legacy burst mode Flash memory controllers. See Figure 34.18, Asynchronous Write Followed by Burst Read (timing diagram).
29.5 Wait Operation
The Wait output on a CellularRAM device is typically connected to a shared, system-level Wait signal (Figure 29.6). The shared Wait signal is used by the processor to coordinate transactions with multiple memories on the synchronous bus.
External Pull-Up/ Pull-Down Resistor
CellularRAM WAIT READY WAIT Processor Other Device WAIT Other Device
Figure 29.6
Wired or Wait Configuration
Once a Read or Write operation has been initiated, Wait goes active to indicate that the CellularRAM device requires additional time before data can be transferred. For Read operations, Wait will remain active until valid data is output from the device. For Write operations, Wait will indicate to the memory controller when data will be accepted into the CellularRAM device. When Wait transitions to an inactive state, the data burst will progress on successive clock edges. CE# must remain asserted during Wait cycles (Wait asserted and Wait configuration BCR[8] = 1). Bringing CE# High during Wait cycles may cause data corruption. (Note that for BCR[8] = 0, the actual Wait cycles end one cycle after Wait de-asserts, and for row boundary crossings, start one cycle after the Wait signal asserts.) When using variable initial access latency (BCR[14] = 0), the Wait output performs an arbitration role for Read or Write operations launched while an on-chip refresh is in progress. If a collision occurs, the Wait pin is asserted for additional clock cycles until the refresh has completed (Figure 29.7 and Figure 29.8). When the refresh operation has completed, the Read or Write operation will continue normally. Wait is also asserted when a continuous Read or Write burst crosses the boundary between 128word rows. The Wait assertion allows time for the new row to be accessed, and permits any pending refresh operations to be performed. Wait will be asserted but should be ignored during asynchronous Read and Write, and page Read operations.
29.6 LB#/UB# Operation
The LB# enable and UB# enable signals support byte-wide data transfers. During Read operations, the enabled byte(s) are driven onto the DQs. The DQs associated with a disabled byte are put into a High-Z state during a Read operation. During Write operations, any disabled bytes will
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not be transferred to the RAM array and the internal value will remain unchanged. During an asynchronous Write cycle, the data to be written is latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first. When both the LB# and UB# are disabled (High) during an operation, the device will disable the data bus from receiving or transmitting data. Although the device will seem to be deselected, it remains in an active mode as long as CE# remains Low.
CLK VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL VOH VOL D[0] D[1] D[2] D[3] High-Z Address Valid
A[22:0]
ADV#
CE#
OE#
WE#
LB#/UB#
WAIT
DQ[15:0]
Additional WAIT states inserted to allow refresh completion.
Legend:
Don't care
Undefined
Note: Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay.
Figure 29.7
Refresh Collision During Read Operation
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CLK
VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL VOH VOL D[0] D[1] D[2] D[3] High-Z Address Valid
A[22:0]
ADV#
CE#
OE#
WE#
LB#/UB#
WAIT
DQ[15:0]
Additional WAIT states inserted to allow refresh completion.
Legend:
Don't care
Note: Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay.
Figure 29.8
Refresh Collision During Write Operation
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30 Low-Power Operation
30.1 Standby Mode Operation
During standby, the device current consumption is reduced to the level necessary to perform the DRAM refresh operation. Standby operation occurs when CE# is High. The device will enter a reduced power state upon completion of a Read or Write operation, or when the address and control inputs remain static for an extended period of time. This mode will continue until a change occurs to the address or control inputs.
30.2 Temperature Compensated Refresh
Temperature compensated refresh (TCR) is used to adjust the refresh rate depending on the device operating temperature. DRAM technology requires increasingly frequent refresh operation to maintain data integrity as temperatures increase. More frequent refresh is required due to increased leakage of the DRAM capacitive storage elements as temperatures rise. A decreased refresh rate at lower temperatures will facilitate a savings in standby current. TCR allows for adequate refresh at four different temperature thresholds (+15C, +45C, +70C, and +85C). The setting selected must be for a temperature higher than the case temperature of the CellularRAM device. For example, if the case temperature is 50C, the system can minimize self refresh current consumption by selecting the +70C setting. The +15C and +45C settings would result in inadequate refreshing and cause data corruption.
30.3 Partial Array Refresh
Partial array refresh (PAR) restricts refresh operation to a portion of the total memory array. This feature enables the device to reduce standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array, one-quarter array, three-quarter array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address map (Table 31.6). Read and Write operations to address ranges receiving refresh will not be affected. Data stored in addresses not receiving refresh will become corrupted. When re-enabling additional portions of the array, the new portions are available immediately upon writing to the RCR.
30.4 Deep Power-Down Operation
Deep power-down (DPD) operation disables all refresh-related activity. This mode is used if the system does not require the storage provided by the CellularRAM device. Any stored data will become corrupted when DPD is enabled. When refresh activity has been re-enabled by rewriting the RCR, the CellularRAM device will require 150s to perform an initialization procedure before normal operations can resume. During this 150s period, the current consumption will be higher than the specified standby levels, but considerably lower than the active current specification. DPD cannot be enabled or disabled by writing to the RCR using the software access sequence; the RCR should be accessed using CRE instead.
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31 Configuration Registers
Two user-accessible configuration registers define the device operation. The bus configuration register (BCR) defines how the CellularRAM interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh configuration register (RCR) is used to control how refresh is performed on the DRAM array. These registers are automatically loaded with default settings during power-up, and can be updated any time the devices are operating in a standby state.
31.1
Access Using CRE
The configuration registers can be written to using either a synchronous or an asynchronous operation when the configuration register enable (CRE) input is High (see Figure 31.1 and Figure 31.2). When CRE is Low, a Read or Write operation will access the memory array. The register values are written via address pins A[21:0]. In an asynchronous Write, the values are latched into the configuration register on the rising edge of ADV#, CE#, or WE#, whichever occurs first; LB# and UB# are Don't Care. The BCR is accessed when A[19] is High; the RCR is accessed when A[19] is Low. For Reads, address inputs other than A[19] are Don't Care, and register bits 15:0 are output on DQ[15:0].
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A[22:0] (except A19)
OPCODE tAVS Select Control Register tAVH
ADDRESS
A19 (Note)
ADDRESS
CRE tAVS tAVH tVPH ADV# tVP tCBPH Initiate Control Register Access CE# tCW
OE# tWP Write Address Bus Value to Control Register WE#
LB#/UB#
DQ[15:0]
DATA VALID
Legend:
Don't care
Note: A[19] = Low to load RCR; A[19] = High to load BCR.
Figure 31.1
Configuration Register Write, Asynchronous Mode Followed by Read
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CLK Latch Control Register Value A[22:0] (except A19) OPCODE tHD tSP A19 (Note 2) tSP CRE tHD tSP ADV# tHD tCSP CE# Latch Control Register Address ADDRESS ADDRESS
tCBPH (Note 3)
OE# tSP WE# tHD LB#/UB# tCEW WAIT High-Z DQ[15:0] High-Z DATA VALID
Legend:
Don't care
Notes:
1. 2. 3. Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay. A[19] = Low to load RCR; A[19] = High to load BCR. CE# must remain Low to complete a burst-of-one Write. Wait must be monitored--additional Wait cycles caused by refresh collisions require a corresponding number of additional CE# Low cycles.
Figure 31.2
Configuration Register Write, Synchronous Mode Followed by Read0
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31.2
Bus Configuration Register
The BCR defines how the CellularRAM device interacts with the system memory bus. Page mode operation is enabled by a bit contained in the RCR. Table 31.1 below describes the control bits in the BCR. At powerup, the BCR is set to 9D4Fh. The BCR is accessed using CRE and A[19] High.
Table 31.1
A[22:20] A19 A[18:16] A15 A14
Bus Configuration Register Definition
A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
22-20
19
18-16
15
14
13
12
11
10
9
8 WAIT Configuration (WC)
7
6
5
4
3 Burst Wrap (BW) (Note)
2
1
0
Reserved
Register Select
Reserved
Operating Mode
Initial Latency
Latency Counter
WAIT Polarity
Reserved
Reserved
Reserved
Output Impedance
Burst Length (BL) (Note)
All must be set to "0"
Must be set to "0"
Must be set to "0"
Must be set to "0"
Must be set to "0" Setting is ignored BCR[5] BCR[4] 0 0 1 1 0 1 0 1 Output Impedance Full Drive (default) 1/2 Drive 1/4 Drive Reserved
BCR[13] BCR[12] BCR[11] Latency Counter 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Code 0-Reserved Code 1-Reserved Code 2 Code 3 (Default) Code 4 Code 5 Code 6 Code 7-Reserved BCR[8] 0 1 BCR[10] WAIT Polarity 0 1 BCR[15] 0 1 BCR[19] 0 1 Register Select Select RCR Select BCR Operating Mode Synchronous burst access mode Asynchronous access mode (default) Active LOW Active HIGH (default) BCR[2] BCR[1] BCR[0] Burst Length (Note) 0 0 0 1 0 1 1 1 Others 1 0 1 1 4 words 8 words 16 words Continuous burst (default) Reserved WAIT Configuration Asserted during delay Asserted one data cycle before delay (default) BCR[3] 0 1 Burst Wrap (Note) Burst wraps within the burst length Burst no wrap (default)
Note: Burst wrap and length apply to Read operations only.
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Table 31.2
Starting Address
Sequence and Burst Length
Burst Wrap
4-word Burst Length 8-word Burst Length Linear
0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6
16-word Burst Length Linear
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0 2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1 3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2 4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3 5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4 6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5 7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6 ... 14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13 15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14
Continuous Burst Linear
0-1-2-3-4-5-6-... 1-2-3-4-5-6-7-... 2-3-4-5-6-7-8-... 3-4-5-6-7-8-9-... 4-5-6-7-8-9-10-... 5-6-7-8-9-10-11-... 6-7-8-9-10-11-12-... 7-8-9-10-11-12-13-... ... 14-15-16-17-18-19-20-... 15-16-17-18-19-20-21... 0-1-2-3-4-5-6-... 1-2-3-4-5-6-7-... 2-3-4-5-6-7-8-... 3-4-5-6-7-8-9-... 4-5-6-7-8-9-10-... 5-6-7-8-9-10-11... 6-7-8-9-10-11-12... 7-8-9-10-11-12-13... ... 14-15-16-17-18-19-20-... 15-16-17-18-19-20-21-...
BCR[3] Wrap (Decimal) Linear
0 1 2 3 4 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2
0
Yes
5 6 7 ... 14 15 0 1 2 3 4 0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6
0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 3-4-5-6-7-8-9-10 4-5-6-7-8-9-10-11 5-6-7-8-9-10-11-12 6-7-8-9-10-11-12-13 7-8-9-10-11-12-13-14
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16 2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-17 3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-18 4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-19 5-6-7-8-9-10-11-12-13-...-15-16-17-18-19-20 6-7-8-9-10-11-12-13-14-...-16-17-18-19-20-21 7-8-9-10-11-12-13-14-...-17-18-19-20-21-22 ... 14-15-16-17-18-19-...-23-24-25-26-27-28-29 5-16-17-18-19-20-...-24-25-26-27-28-29-30
1
No
5 6 7 ... 14 15
31.2.1
Burst Length (BCR[2:0]): Default = Continuous Burst
Burst lengths define the number of words the device outputs during burst Read operations. The device supports a burst length of 4, 8, or 16 words. The device can also be set in continuous burst mode where data is accessed sequentially without regard to address boundaries. Enabling burst no-wrap with BCR[3] = 1 overrides the burst-length setting.
31.2.2
Burst Wrap (BCR[3]): Default = No Wrap
The burst-wrap option determines if a 4-, 8-, or 16-word Read burst wraps within the burst length or steps through sequential addresses. If the wrap option is not enabled, the device accesses data from sequential addresses without regard to burst boundaries. When continuous burst operation is selected, the internal address wraps to 000000h if the burst goes past the last address. Enabling burst nowrap (BCR[3] = 1) overrides the burst-length setting.
31.2.3
Output Impedance (BCR[5:4]): Default = Outputs Use Full Drive Strength
The output driver strength can be altered to full, one-half, or one-quarter strength to adjust for different data bus loading scenarios. The reduced-strength options are intended for stacked chip (Flash + CellularRAM) environments when there is a dedicated memory bus. The reduced-drive-
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strength option minimizes the noise generated on the data bus during Read operations. Normal output drive strength should be selected when using a discrete CellularRAM device in a more heavily loaded data bus environment. Outputs are configured at full drive strength during testing.
Table 31.3
BCR[5] 0 0 1 1
Output Impedance
DRIVE STRENGTH Full 1/2 1/4 Reserved
BCR[4] 0 1 0 1
31.2.4
Wait Configuration (BCR[8]): Default = Wait Transitions One Clock Before Data Valid/Invalid
The Wait configuration bit is used to determine when Wait transitions between the asserted and the de-asserted state with respect to valid data presented on the data bus. The memory controller will use the Wait signal to coordinate data transfer during synchronous Read and Write operations. When BCR[8] = 0, data will be valid or invalid on the clock edge immediately after Wait transitions to the de-asserted or asserted state, respectively (Figure 31.3 and Figure 31.5). When A8 = 1, the Wait signal transitions one clock period prior to the data bus going valid or invalid (Figure 31.4).
31.2.5
Wait Polarity (BCR[10]): Default = Wait Active High
The Wait polarity bit indicates whether an asserted Wait output should be High or Low. This bit will determine whether the Wait signal requires a pull-up or pull-down resistor to maintain the deasserted state.
CLK
WAIT
DQ[15:0]
High-Z
Data[0]
Data[1]
Data immediately valid (or invalid)
Note: Data valid/invalid immediately after Wait transitions (BCR[8] = 0). See Figure 31.5.
Figure 31.3
Wait Configuration (BCR[8] = 0)
CLK
WAIT
DQ[15:0]
High-Z
Data[0]
Data valid (or invalid) after one clock delay
Note: Valid/invalid data delayed for one clock after Wait transitions (BCR[8] = 1). See Figure 31.5.
Figure 31.4
Wait Configuration (BCR[8] = 1)
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CLK
WAIT
BCR[8] = 0 DATA VALID IN CURRENT CYCLE BCR[8] = 1 DATA VALID IN NEXT CYCLE
WAIT
DQ[15:0]
D[0]
D[1]
D[2]
D[3]
D[4]
Legend:
Don't care
Note: Non-default BCR setting: Wait active Low.
Figure 31.5 31.2.6
Wait Configuration During Burst Operation
Latency Counter (BCR[13:11]): Default = Three-Clock Latency
The latency counter bits determine how many clocks occur between the beginning of a Read or Write operation and the first data value transferred. Latency codes from two (three clocks) to six (seven clocks) are allowed (see Table 31.4 and Figure 31.6 below).
Table 31.4
Latency Configuration Code 2 (3 clocks) 3 (4 clocks)--default 4 (5 clocks)
Variable Latency Configuration Codes
Latency (Note) Normal 2 3 4 Refresh Collision 4 6 8 Max Input Clk Frequency (MHz) 70 ns/80 MHz 75 (13.0 ns) 80 (12.5 ns) 85 ns/66 MHz 44 (22.7 ns) 66 (15.2 ns)
BCR[13:11] 010 011 100
Note: Latency is the number of clock cycles from the initiation of a burst operation until data appears. Data is transferred on the next clock cycle.
VIH VIL VIH VIL VIH VIL Code 2 A/DQ[15:0] VOH VOL Code 3 A/DQ[15:0] VOH VOL Code 4 A/DQ[15:0] VOH VOL Valid Output Valid Output Valid Output (Default) Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Address
CLK
A[21:0]
ADV#
Legend:
Don't care
Undefined
Figure 31.6 February 17, 2005 S75WS-N-00_A0
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31.2.7
Operating Mode (BCR[15]): Default = Asynchronous Operation
The operating mode bit selects either synchronous burst operation or the default asynchronous mode of operation.
31.3
Refresh Configuration Register
The refresh configuration register (RCR) defines how the CellularRAM device performs its transparent self refresh. Altering the refresh parameters can dramatically reduce current consumption during standby mode. Page mode control is also embedded into the RCR. Table 31.5 below describes the control bits used in the RCR. At power-up, the RCR is set to 0070h. The RCR is accessed using CRE and A[19] Low.
Table 31.5
A[22:20] A19 A[18:8]
Refresh Configuration Register Mapping
A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
22-20 Reserved
19 Register Select
18-8 Reserved
7 Page
6 TCR
5
4 DPD
3 Reserved
2 PAR
1
0
Read Configuration Register
All must be set to "0"
All must be set to "0"
Must be set to "0"
RCR[19] Register Select 0 1 Select RCR Select BCR
RCR[2] RCR[1] RCR[0] 0 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
Refresh Coverage Full array (default) Bottom 1/2 array Bottom 1/4 array Bottom 1/8 array None of array Top 1/2 array Top 1/4 array Top 3/4 array
RCR[7] 0 1
Page Mode Enable/Disable Page Mode Disabled (default) Page Mode Enable
0 1 1 1 1 RCR[4] 0 1
RCR[6] 1 0 0 1
RCR[5] 1 0 1 0
Maximum Case Temp +85C (default) +70C +45C +15C
Deep Power-Down DPD Enable DPD Disable (default)
31.3.1
Partial Array Refresh (RCR[2:0]): Default = Full Array Refresh
The PAR bits restrict refresh operation to a portion of the total memory array. This feature allows the device to reduce standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array, one-quarter array, threequarters array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address map (see Table 31.6 through Table 31.8).
Table 31.6
RCR[2] 0 0 0 0 1 1 RCR[1] 0 0 1 1 0 0 RCR[0] 0 1 0 1 0 1
128Mb Address Patterns for PAR (RCR[4] = 1)
Active Section Full die One-half of die One-quarter of die One-eighth of die None of die One-half of die Address Space 000000h-7FFFFFh 000000h-3FFFFFh 000000h-1FFFFFh 000000h-0FFFFFh 0 400000h-7FFFFFh Size 8 Meg x 16 4 Meg x 16 2 Meg x 16 1 Meg x 16 0 Meg x 16 4 Meg x 16 Density 128Mb 64Mb 32Mb 16Mb 0Mb 64Mb
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Table 31.6
RCR[2] 1 1 RCR[1] 1 1
128Mb Address Patterns for PAR (RCR[4] = 1) (Continued)
Active Section One-quarter of die One-eighth of die Address Space 600000h-7FFFFFh 700000h-7FFFFFh Size 2 Meg x 16 1 Meg x 16 Density 32Mb 16Mb
RCR[0] 0 1
Table 31.7
RCR[2] 0 0 0 0 1 1 1 1 RCR[1] 0 0 1 1 0 0 1 1 RCR[0] 0 1 0 1 0 1 0 1
64Mb Address Patterns for PAR (RCR[4] = 1)
Active Section Full die One-half of die One-quarter of die One-eighth of die None of die One-half of die One-quarter of die One-eighth of die Address Space 000000h-3FFFFFh 000000h-2FFFFFh 000000h-1FFFFFh 000000h-0FFFFFh 0 100000h-3FFFFFh 200000h-3FFFFFh 300000h-3FFFFFh Size 4 Meg x 16 3 Meg x 16 2 Meg x 16 1 Meg x 16 0 Meg x 16 3 Meg x 16 2 Meg x 16 1 Meg x 16 Density 64Mb 48Mb 32Mb 16Mb 0Mb 48Mb 32Mb 16Mb
Table 31.8
RCR[2] 0 0 0 0 1 1 1 1 RCR[1] 0 0 1 1 0 0 1 1 RCR[0] 0 1 0 1 0 1 0 1
32Mb Address Patterns for PAR (RCR[4] = 1)
ACTIVE SECTION Full die One-half of die One-quarter of die One-eighth of die None of die One-half of die One-quarter of die One-eighth of die ADDRESS SPACE 000000h-1FFFFFh 000000h-17FFFFh 000000h-0FFFFFh 000000h-07FFFFh 0 080000h-1FFFFFh 100000h-1FFFFFh 180000h-1FFFFFh SIZE 2 Meg x 16 1.5 Meg x 16 1 Meg x 16 512K x 16 0 Meg x 16 1.5 Meg x 16 1 Meg x 16 512K x 16 DENSITY 32Mb 24Mb 16Mb 8Mb 0Mb 24Mb 16Mb 8Mb
31.3.2
Deep Power-Down (RCR[4]): Default = DPD Disabled
The deep power-down bit enables and disables all refresh-related activity. This mode is used if the system does not require the storage provided by the CellularRAM device. Any stored data will become corrupted when DPD is enabled. When refresh activity has been re-enabled, the CellularRAM device will require 150s to perform an initialization procedure before normal operations can resume. Deep power-down is enabled when RCR[4] = 0, and remains enabled until RCR[4] is set to 1.
31.3.3
Temperature Compensated Refresh (RCR[6:5]): Default = +85C Operation
The TCR bits allow for adequate refresh at four different temperature thresholds (+15C, +45C, +70C, and +85C). The setting selected must be for a temperature higher than the case temperature of the CellurlarRAM device. If the case temperature is +50C, the system can minimize self refresh current consumption by selecting the +70C setting. The +15C and +45C settings would result in inadequate refreshing and cause data corruption.
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31.3.4
Page Mode Operation (RCR[7]): Default = Disabled
The page mode operation bit determines whether page mode is enabled for asynchronous Read operations. In the power-up default state, page mode is disabled.
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32 Absolute Maximum Ratings
Voltage to Any Ball Except VCC, VCCQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . Relative to VSS-0.50V to (4.0V or VCCQ + 0.3V, whichever is less) Voltage on VCC Supply Relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2V to +2.45V Voltage on VCCQ Supply Relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2V to +2.45V Storage Temperature (plastic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +150C Operating Temperature (case) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wireless-25C to +85C
Note: *Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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33 DC Characteristics
Table 33.1
Description Supply Voltage I/O Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current IOH = -0.2mA IOL = +0.2mA VIN = 0 to VCCQ OE# = VIH or Chip Disabled
Electrical Characteristics and Operating Conditions
Conditions VCC VCCQ VIH VIL VOH VOL ILI ILO Operating Current W: 1.8V J: 1.5V Symbol Min 1.70 1.70 1.35 VCCQ - 0.4 -0.20 0.80 VCCQ 0.20 VCCQ 1 1 Max 1.95 1.95 1.65 VCCQ + 0.2 0.4 Units V V V V V V V A A 2 3 4 4 Notes
Asynchronous Random Read
-70 VIN = VCCQ or 0V Chip Enabled, IOUT = 0 ICC1 -85 -70 -85 80 MHz VIN = VCCQ or 0V Chip Enabled, IOUT = 0 ICC1 66 MHz 80 MHz 66 MHz VIN = VCCQ or 0V Chip Enabled ICC2 -70 -85 128 M
25 20 15 12 35 30 18 15 25 20 180 120 110 A 6 mA mA 5 mA 5
Asynchronous Page Read
Initial Access, Burst Read
Continuous Burst Read
Write Operating Current
Standby Current
VIN = VCCQ or 0V CE# = VCCQ
ISB
64 M 32 M
Notes:
1. 2. 3. 4. 5. 6. Wireless Temperature (-25C < TC < +85C); Industrial Temperature (-40C < TC < +85C). Input signals may overshoot to VCCQ + 1.0V for periods less than 2ns during transitions. Input signals may undershoot to VSS - 1.0V for periods less than 2ns during transitions. BCR[5:4] = 00b. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add the current required to drive output capacitance expected in the actual system. ISB (MAX) values measured with PAR set to FULL ARRAY and TCR set to +85C. To achieve Low standby current, all inputs must be driven to either VCCQ or VSS.
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Table 33.2
Temperature Compensated Refresh Specifications and Conditions
Max Case Temperature +85C 64 Mb +70C +45C +15C +85C 32 Mb +70C +45C +15C Standard Power (No Desig.) 120 105 85 70 110 95 80 70 A
Description
Conditions
Symbol
Density
Units
Temperature Compensated Refresh Standby Current
VIN = VCCQ or 0V, CE# = VCCQ
ITCR
Note: IPAR (MAX) values measured with TCR set to 85C.
Table 33.3
Partial Array Refresh Specifications and Conditions
Array Partition Full 1/2 64 Mb 1/4 1/8 0 Standard Power (No Desig.) 120 115 110 105 70 110 105 100 95 70 180 50 A
Description
Conditions
Symbol
Density
Units
Partially Array Refresh Standby Current
VIN = VCCQ or 0V, CE# = VCCQ
IPAR 32 Mb
Full 1/2 1/4 1/8 0 128 Mb Full 0
Note:IPAR (MAX) values measured with TCR set to 85C.
Table 33.4
Description Deep Power-down
Deep Power-Down Specifications
Symbol IZZ Typ 10 Units A
Conditions VIN = VCCQ or 0V; +25C; VCC = 1.8V
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34 AC Characteristics
VCC Q Input (Note 1) VSS VCCQ /2 (Note 2) Test Points VCCQ/2 (Note 3) Output
Notes:
1. 2. 3. AC test inputs are driven at VCCQ for a logic 1 and VSS for a logic 0. Input rise and fall times (10% to 90%) < 1.6ns. Input timing begins at VCCQ/2. Output timing ends at VCCQ/2.
Figure 34.1
AC Input/Output Reference Waveform
VCCQ R1 DUT 30pF R2 Test Point
Note: All tests are performed with the outputs configured for full drive strength (BCR[5] = 0).
Figure 34.2
Output Load Circuit
Table 34.1
VCCQ 1.8V
Output Load Circuit
R1/R2 2.7K
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Table 34.2
Asynchronous Read Cycle Timing Requirements
85ns/66 MHz 70ns/80 MHz Min Max 70 70 20 5 10 85 8 10 5 4 1 7.5 85 10 8 10 20 5 8 5 25 85 10 10 5 20 70 10 10 5 8 10 20 10 8 1 10 5 4 7.5 70 70 8 ns ns ns ns ns ns ns ns ns s ns ns ns ns ns ns ns ns ns ns ns ns ns 4 3 4 3 2 4 3 Units Notes
Parameter Address Access Time ADV# Access Time Page Access Time Address Hold from ADV# High Address Setup to ADV# High LB#/UB# Access Time LB#/UB# Disable to DQ High-Z Output LB#/UB# Enable to Low-Z Output CE# High between Subsequent Mixed-Mode Operations Maximum CE# Pulse Width CE# Low to Wait Valid Chip Select Access Time CE# Low to ADV# High Chip Disable to DQ and Wait High-Z Output Chip Enable to Low-Z Output Output Enable to Valid Output Output Hold from Address Change Output Disable to DQ High-Z Output Output Enable to Low-Z Output Page Cycle Time Read Cycle Time ADV# Pulse Width Low ADV# Pulse Width High
Notes:
1. 2. 3. 4. 5.
Symbol tAA tAADV tAPA tAVH tAVS tBA tBHZ tBLZ tCBPH tCEM tCEW tCO tCVS tHZ tLZ tOE tOH tOHZ tOLZ tPC tRC tVP tVPH
Min
Max 85 85 25
5 10
All tests are performed with the outputs configured for full drive strength (BCR[5] = 0). See How Extended Timings Impact CellularRAMTM Operation below. High-Z to Low-Z timings are tested with the circuit shown in Figure 34.2. The Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL. Low-Z to High-Z timings are tested with the circuit shown in Figure 34.2. The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2.
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Table 34.3
Burst Read Cycle Timing Requirements
70ns/80 MHz 85ns/66 MHz Min Max 55 11 10 20 5 1 12.5 4 2 8 1.6 9 3 2 2 3 8 5 3 5 3 8 5 3 2 2 3 8 7.5 5 1 15 5 2 8 1.6 11 8 5 7.5 20 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2 3 2 Notes
Parameter Burst to Read Access Time (Variable Latency) CLK to Output Delay Address Setup to ADV# High Burst OE# Low to Output Delay CE# High between Subsequent Mixed-Mode Operations CE# Low to Wait Valid CLK Period CE# Setup Time to Active CLK Edge Hold Time from Active CLK Edge Chip Disable to DQ and Wait High-Z Output CLK Rise or Fall Time CLK to Wait Valid CLK to DQ High-Z Output CLK to Low-Z Output Output Hold from CLK CLK High or Low Time Output Disable to DQ High-Z Output Output Enable to Low-Z Output Setup Time to Active CLK Edge
Notes:
1. 2. 3.
Symbol tABA tACLK tAVS tBOE tCBPH tCEW tCLK tCSP tHD tHZ tKHKL tKHTL tKHZ tKLZ tKOH tKP tOHZ tOLZ tSP
Min
Max 35 9
10
All tests are performed with the outputs configured for full drive strength (BCR[5] = 0). Low-Z to High-Z timings are tested with the circuit shown in Figure 34.2. The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2. High-Z to Low-Z timings are tested with the circuit shown in Figure 34.2. The Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL.
172
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Table 34.4
Asynchronous Write Cycle Timing Requirements
70 ns/80 MHz 85 ns/66 MHz Min 0 5 10 85 85 4 1 70 10 70 0 23 8 10 5 10 10 70 70 8 46 10 0 55 10 0 10 5 10 10 85 85 8 7.5 1 85 10 85 0 23 8 4 7.5 ns ns ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2 1 3 3 1 1 Max Units ns ns Notes
Parameter Address and ADV# Low Setup Time Address Hold from ADV# Going High Address Setup to ADV# Going High Address Valid to End of Write LB#/UB# Select to End of Write Maximum CE# Pulse Width CE# Low to Wait Valid Async Address-to-Burst Transition Time CE# Low to ADV# High Chip Enable to End of Write Data Hold from Write Time Data Write Setup Time Chip Disable to Wait High-Z Output Chip Enable to Low-Z Output End Write to Low-Z Output ADV# Pulse Width ADV# Pulse Width High ADV# Setup to End of Write Write Cycle Time Write to DQ High-Z Output Write Pulse Width Write Pulse Width High Write Recovery Time
Notes:
1. 2. 3.
Symbol tAS tAVH tAVS tAW tBW tCEM tCEW tCKA tCVS tCW tDH tDW tHZ tLZ tOW tVP tVPH tVS tWC tWHZ tWP tWPH tWR
Min 0 5 10 70 70
Max
See How Extended Timings Impact CellularRAMTM Operation below. Low-Z to High-Z timings are tested with the circuit shown in Figure 34.2. The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2. High-Z to Low-Z timings are tested with the circuit shown in Figure 34.2. The Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL.
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Table 34.5
Burst Write Cycle Timing Requirements
70ns/80 MHz 85ns/66 MHz Min 5 7.5 1 15 5 2 8 1.6 9 3 3 3 3 8 1.6 11 7.5 Max Units ns ns ns ns ns ns ns ns ns ns Notes
Parameter CE# High between Subsequent Mixed-Mode Operations CE# Low to Wait Valid Clock Period CE# Setup to CLK Active Edge Hold Time from Active CLK Edge Chip Disable to Wait High-Z Output CLK Rise or Fall Time Clock to Wait Valid CLK High or Low Time Setup Time to Activate CLK Edge
Symbol tCBPH tCEW tCLK tCSP tHD tHZ tKHKL tKHTL tKP tSP
Min 5 1 12.5 4 2
Max
34.1
Timing Diagrams
VCC (MIN) tPU Device ready for normal operation
VCC, VCCQ = 1.7V
Figure 34.3 Table 34.1
Initialization Period
Initialization Timing Parameters
70ns/80 MHz 85ns/66 MHz Min Max 150 Units s Notes
Parameter Initialization Period (required before normal operations)
Symbol tPU
Min
Max 150
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t RC A[22:0] V IH V IL t AA V IH V IL t CBPH CE# V IH V IL t CO t BA LB#/UB# V IH V IL t OE OE# V IH V IL V IH V IL t OLZ t BLZ t LZ V OH V OL t CEW V IH V IL Legend: Don't Care Undefined High-Z High-Z t OHZ t BHZ t HZ VALID ADDRESS
ADV#
WE#
DQ[15:0]
VALID OUTPUT t HZ High-Z
WAIT
Figure 34.4
Asynchronous Read
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Table 34.2
Asynchronous Read Timing Parameters
85ns/66 MHz Max 70 70 8 Min Max 85 85 8 10 5 7.5 70 8 8 10 20 8 20 8 5 85 1 7.5 Units ns ns ns ns ns ns ns ns ns ns ns ns ns
70ns/80 MHz Symbol tAA tBA tBHZ tBLZ tCBPH tCEW tCO tHZ tLZ tOE tOHZ tOLZ tRC 5 70 10 10 5 1 Min
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A[22:0]
V IH V IL
VALID ADDRESS t AA t AVS t AVH
t VPH ADV# V IH V IL
t AADV t VP t CBPH t CVS t HZ
CE#
V IH V IL t CO t BA t BHZ
LB#/UB#
V IH V IL t OE t OHZ
OE#
V IH V IL V IH V IL t OLZ t BLZ t LZ V OH V OL t CEW V IH V IL Legend: Don't Care Undefined High-Z High-Z
WE#
DQ[15:0]
VALID OUTPUT t HZ High-Z
WAIT
Figure 34.5
Asynchronous Read Using ADV#
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Table 34.3 Asynchronous Read Timing Parameters Using ADV#
70ns/80 MHz Symbol tAA tAADV tCVS tAVH tAVS tBA tBHZ tBLZ tCBPH tCEW tCO tCVS tHZ tLZ tOE tOHZ tOLZ tVP tVPH 5 10 10 10 20 8 5 10 10 10 8 10 20 8 10 5 1 7.5 70 10 8 10 5 10 70 8 10 5 1 7.5 85 Min Max 70 70 10 5 10 85 8 Min 85ns/66 MHz Max 85 85 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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t RC A[22:0] V IH V IL V IH V IL VALID ADDRESS t AA V IH V IL t CEM t CBPH CE# V IH V IL t BA LB#/UB# V IH V IL t OE OE# V IH V IL V IH V IL t BLZ t LZ V OH V OL t CEW V IH V IL Legend: Don't Care Undefined High-Z High-Z t OLZ t APA t OH t OHZ t BHZ t CO t CBPH t HZ VALID ADDRESS
A[3:0]
VALID ADDRESS t PC
VALID ADDRESS
VALID ADDRESS
ADV#
WE#
DQ[15:0]
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT t HZ High-Z
WAIT
Figure 34.6 Page Mode Read
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Table 34.4
Asynchronous Read Timing Parameters--Page Mode Operation
70ns/80 MHz 85ns/66 MHz Max 70 20 70 8 10 5 4 1 7.5 70 8 10 20 5 8 5 20 70 5 25 85 5 8 10 20 1 10 5 4 7.5 85 8 Min Max 85 25 85 8 Units ns ns ns ns ns ns s ns ns ns ns ns ns ns ns ns ns
Symbol tAA tAPA tBA tBHZ tBLZ tCBPH tCEM tCEW tCO tHZ tLZ tOE tOH tOHZ tOLZ tPC tRC
Min
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t CLK V IH V IL t KHKL t SP A[22:0] V IH V IL t HD
t KP
t KP
CLK
VALID ADDRESS t SP t HD
ADV#
V IH V IL t HD t CSP t ABA t HZ
CE#
V IH V IL t BOE t OHZ
OE#
V IH V IL
t SP WE# V IH V IL t SP LB#/UB# V IH V IL t CEW V OH V OL High-Z
t HD
t OLZ
t HD
t KHTL High-Z
WAIT
t ACLK DQ[15:0] V OH V OL High-Z
t KOH VALID OUTPUT
READ Burst Identified (WE# = HIGH)
Legend:
Don't Care
Undefined
Note: Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay.
Figure 34.7
Single-Access Burst Read Operation--Variable Latency
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Table 34.5
Burst Read Timing Parameters--Single Access, Variable Latency
70ns/80 MHz 85ns/66 MHz Max 35 9 20 1 7.5 1 15 5 2 8 1.6 9 2 3 8 5 3 5 3 2 3 8 8 1.6 11 Min Max 55 11 20 7.5 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Symbol tABA tACLK tBOE tCEW tCLK tCSP tHD tHZ tKHKL tKHTL tKOH tKP tOHZ tOLZ tSP
Min
12.5 4 2
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t KHKL CLK V IH V IL t SP A[22:0] V IH V IL t HD
t CLK
t KP
t KP
Valid Address t SP t HD
ADV#
V IH V IL t CSP t ABA t HD t CBPH
CE#
V IH V IL t HZ
OE#
V IH V IL t SP t HD t OLZ
t BOE
t OHZ
WE#
V IH V IL t SP t HD
LB#/UB#
V IH V IL t CEW V OH V OL t KOH t ACLK High-Z t KHTL High-Z
WAIT
DQ[15:0]
V OH V OL
High-Z
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
READ Burst Identified (WE# = HIGH)
Legend:
Don't Care
Undefined
Note: Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay.
Figure 34.8
Four-word Burst Read Operation--Variable Latency
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Table 34.6
Burst Read Timing Parameters--4-word Burst
85ns/66 MHz Max 35 9 20 Min Max 55 11 20 5 7.5 1 15 5 2 8 1.6 9 8 1.6 11 2 3 8 8 5 3 7.5 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
70ns/80 MHz Symbol tABA tACLK tBOE tCBPH tCEW tCLK tCSP tHD tHZ tKHKL tKHTL tKOH tKP tOHZ tOLZ tSP 5 3 2 3 5 1 12.5 4 2 Min
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t CLK V IH V IL t SP A[22:0] V IH V IL t HD
CLK
Valid Address t SP t HD
ADV#
V IH V IL t CSP t HD t CBPH
CE#
V IH V IL t HZ
OE#
V IH V IL t SP t HD t OLZ
t BOE
t OHZ
WE#
V IH V IL t SP t HD
LB#/UB#
V IH V IL t CEW V OH V OL t KOH t ACLK t KHTL t KHTL t KHTL High-Z t KHTL High-Z
WAIT
DQ[15:0]
V OH V OL
High-Z
VALID OUTPUT
VALID OUTPUT
High-Z
VALID OUTPUT
READ Burst Identified (WE# = HIGH)
Legend:
Don't Care
Undefined
Note: Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay.
Figure 34.9
Four-word Burst Read Operation (with LB#/UB#)
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Table 34.7
Burst Read Timing Parameters--4-word Burst with LB#/UB#
70ns/80 MHz 85ns/66 MHz Max 9 20 Min Max 11 20 5 7.5 1 15 5 2 8 9 8 11 3 2 2 8 8 5 3 8 5 7.5 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Symbol tACLK tBOE tCBPH tCEW tCLK tCSP tHD tHZ tKHTL tKHZ tKLZ tKOH tOHZ tOLZ tSP
Min
5 1 12.5 4 2
3 2 2
8 5
5 3
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t CLK V IH V IL t SP A[22:0] V IH V IL t HD Valid Address
CLK
Valid Address t HD t SP
ADV#
V IH V IL t CBPH t CSP t HZ
CE#
V IH V IL t OHZ t OHZ
OE#
V IH V IL t SP t HD
(Note 2)
WE#
V IH V IL t SP t HD
LB#/UB#
V IH V IL t CEW V IH V IL t KOH t ACLK t OLZ t BOE High-Z t OLZ t BOE High-Z
WAIT
DQ[15:0]
V OH V OL
High-Z
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
Legend:
Don't Care
Undefined
Notes:
1. 2.
Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay. OE# can stay Low during burst suspend. If OE# is Low, DQ[15:0] will continue to output valid data.
Figure 34.10 Table 34.8
Refresh Collision During Write Operation
Burst Read Timing Parameters--Burst Suspend
85ns/66 MHz Max 9 20 Min Max 11 20 5 15 5 2 8 8 2 8 8 5 Units ns ns ns ns ns ns ns ns ns ns
70ns/80 MHz Symbol tACLK tBOE tCBPH tCLK tCSP tHD tHZ tKOH tOHZ tOLZ 5 2 5 12.5 4 2 Min
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Table 34.8
Burst Read Timing Parameters--Burst Suspend (Continued)
70ns/80 MHz 85ns/66 MHz Max Min 3 Max Units ns
Symbol tSP
Min 3
CLK
V IH V IL t CLK
A[22:0]
V IH V IL V IH V IL V IH V IL V IH V IL V IH V IL V IH V IL t KHTL t KHTL t OHZ
ADV#
LB#/UB#
CE#
OE#
WE#
WAIT
V OH V OL
(Note 2)
t ACLK DQ[15:0] V OH V OL VALID OUTPUT VALID OUTPUT VALID OUTPUT
t KOH VALID OUTPUT
Legend:
Don't Care
Notes:
1. 2.
Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay. Wait will assert LC + 1 or 2LC + 1 cycles for variable latency (depending upon refresh status).
Figure 34.9.
Continuous Burst Read Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition Table 34.10 Burst Read Timing Parameters--BCR[8] = 0
85ns/66 MHz Max 9 12.5 9 2 2 15 11 Min Max 11 Units ns ns ns ns
70ns/80 MHz Symbol tACLK tCLK tKHTL tKOH Min
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t AA A[22:0] V IH V IL VALID ADDRESS t AW t AS V IH V IL t CEM t CW CE# V IH V IL t BW LB#/UB# V IH V IL V IH V IL t WPH WE# V IH V IL t DW DQ[15:0] V IH IN V IL High-Z VALID INPUT t DH t WP t WR
ADV#
OE#
t LZ
t WHZ
DQ[15:0] V OH OUT V OL t CEW V IH V IL High-Z
t HZ High-Z
WAIT
Legend:
Don't Care
Figure 34.11
CE#-Controlled Asynchronous Write
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Table 34.11
Asynchronous Write Timing Parameters--CE#-Controlled
70ns/80 MHz 85ns/66 MHz Max Min 0 85 85 4 4 1 85 0 23 8 8 10 85 8 8 55 10 0 7.5 Max Units ns ns ns s ns ns ns ns ns ns ns ns ns ns ns
Symbol tAS tAW tBW tCEM tCEW tCW tDH tDW tHZ tLZ tWC tWHZ tWP tWPH tWR
Min 0 70 70
1 70 0 23
7.5
10 70
46 10 0
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t WC A[22:0] V IH V IL VALID ADDRESS t AW t AS V IH V IL t CEM t CW CE# V IH V IL t BW LB#/UB# V IH V IL V IH V IL t WPH WE# V IH V IL t DW DQ[15:0] V IH IN V IL High-Z VALID INPUT t DH t WP t WR
ADV#
OE#
t LZ
t WHZ
DQ[15:0] V OH OUT V OL t CEW V IH V IL High-Z
t HZ High-Z
WAIT
Legend:
Don't Care
Figure 34.12
LB#/UB#-Controlled Asynchronous Write
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Table 34.12
Asynchronous Write Timing Parameters--LB#/UB#-Controlled
70ns/80 MHz 85ns/66 MHz Max Min 0 85 85 4 1 7.5 1 85 0 23 8 8 10 85 8 8 55 10 0 4 7.5 Max Units ns ns ns s ns ns ns ns ns ns ns ns ns ns ns
Symbol tAS tAW tBW tCEM tCEW tCW tDH tDW tHZ tLZ tWC tWHZ tWP tWPH tWR
Min 0 70 70
70 0 23
10 70
46 10 0
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t WC A[22:0] V IH V IL VALID ADDRESS t AW t WR V IH V IL t CEM t CW CE# V IH V IL t BW LB#/UB# V IH V IL V IH V IL t AS t WPH WE# V IH V IL t DW DQ[15:0] V IH IN V IL t LZ DQ[15:0] V OH OUT V OL t CEW V IH V IL Legend: High-Z t HZ High-Z High-Z t DH t WP
ADV#
OE#
VALID INPUT t WHZ t OW
WAIT
Don't Care
Figure 34.13
WE#-Controlled Asynchronous Write
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Table 34.13 Asynchronous Write Timing Parameters--WE#-Controlled
70ns/80 MHz Symbol tAS tAW tBW tCEM tCEW tCW tDH tDW tHZ tLZ tOW tWC tWHZ tWP tWPH tWR 46 10 0 10 5 70 8 55 10 0 1 70 0 23 8 10 5 85 8 Min 0 70 70 4 7.5 1 85 0 23 8 Max Min 0 85 85 4 7.5 85ns/66 MHz Max Units ns ns ns s ns ns ns ns ns ns ns ns ns ns ns ns
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A[22:0]
V IH V IL
VALID ADDRESS t AVS t AVH t VS t VPH t AS t VP
ADV#
V IH V IL t AS t AW t CEM t CW
CE#
V IH V IL t BW
LB#/UB#
V IH V IL V IH V IL
OE#
t WP WE# V IH V IL t DW DQ[15:0] V IH IN V IL t LZ DQ[15:0] V OH OUT V OL t CEW V IH V IL Legend: High-Z t HZ High-Z
t WPH
t DH
VALID INPUT t WHZ t OW
WAIT
High-Z
Don't Care
Figure 34.14
Asynchronous Write Using ADV#
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Table 34.14
Asynchronous Write Timing Parameters Using ADV#
85ns/66 MHz Max Min 0 5 10 85 85 4 4 1 85 0 23 8 8 10 5 0 10 10 85 8 8 55 10 7.5 Max Units ns ns ns ns ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns
70ns/80 MHz Symbol tAS tAVH tAVS tAW tBW tCEM tCEW tCW tDH tDW tHZ tLZ tOW tAS tVP tVPH tVS tWHZ tWP tWPH 46 10 10 5 0 10 10 70 1 70 0 23 Min 0 5 10 70 70
7.5
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t KHKL t CLK CLK V IH V IL t SP A[22:0] V IH V IL t HD t KP t KP
Valid Address t SP t HD
ADV#
V IH V IL t SP t HD
LB#/UB#
V IH V IL t CSP t HD t CBPH
CE#
V IH V IL V IH V IL V IH V IL t CEW V IH V IL t SP t HD D[2] D[3] D[0] High-Z (Note 2) t KHTL t OHZ t HZ High-Z t SP t HD
OE#
WE#
WAIT
DQ[15:0]
V OH V OL
D[1]
READ Burst Identified (WE# = LOW)
Legend:
Don't Care
Notes:
1.
Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay; burst length four; burst wrap enabled.
Figure 34.15
Burst Write Operation
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Table 34.15
70ns/80 MHz Symbol tCBPH tCEW tCLK tCSP tHD tHZ tKHKL tKHTL tKP tSP 3 3 Min 5 1 12.5 4 2
Burst Write Timing Parameters
85ns/66 MHz Max Min 5 7.5 1 15 5 2 8 1.6 9 3 3 8 1.6 11 7.5 Max Units ns ns ns ns ns ns ns ns ns ns
CLK
V IH V IL t CLK
A[22:0]
V IH V IL V IH V IL V IH V IL V IH V IL V IH V IL V IH V IL V OH V OL t SP t HD
Valid Input Valid Input D[n+3] D[n+2]
ADV#
LB#/UB#
CE#
WE#
t OHZ
OE#
t KHTL
(Note 2)
t KHTL
WAIT
DQ[15:0]
V OH V OL
Valid Input Valid Input D[n] D[n+1]
END OF ROW
Legend:
Don't Care
Notes:
1. 2.
Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay. Wait will assert LC + 1 or 2LC + 1 cycles for variable latency (depending upon refresh status).
Figure 34.16 198
Continuous Burst Write Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005
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Table 34.16
Burst Write Timing Parameters--BCR[8] = 0
85ns/66 MHz Max Min 15 2 8 3 11 3 Max Units ns ns ns ns
70ns/80 MHz Symbol tCLK tHD tKHTL tSP Min 12.5 2
t CLK CLK V IH V IL t SP A[22:0] V IH V IL t HD t SP t HD
Valid Address
Valid Address t SP
t SP ADV# V IH V IL
t HD
t HD
t SP LB#/UB# V IH V IL t CSP CE# V IH V IL
t HD
t HD
t CBPH
(Note 2) V IH V IL t SP WE# V IH V IL V OH V OL t SP DQ[15:0] V IH V IL High-Z t HD D[1] D[2] D[3] High-Z t HD
t CSP
t OHZ
OE#
t SP
t HD
t BOE
WAIT
High-Z
t ACLK V OH V OL High-Z
t KOH Valid Output Valid Output Valid Output Valid Output
D[0]
Legend:
Don't Care
Undefined
Notes:
1. 1. Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay. To allow self-refresh operations to occur between transactions, CE# must remain High for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. CE# can stay Low between burst Read and burst Write operations. See How Extended Timings Impact CellularRAMTM Operation for restrictions on the maximum CE# Low time (tCEM).
Figure 34.17 Table 34.17
Burst Write Followed by Burst Read
Write Timing Parameters--Burst Write Followed by Burst Read
70ns/80 MHz 85ns/66 MHz Max Min 5 20 20 15 5 2 3 20 20 Max Units ns ns ns ns ns
Symbol tCBPH tCLK tCSP tHD tSP
Min 5 12.5 4 2 3
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Table 34.18
Read Timing Parameters--Burst Write Followed by Burst Read
70ns/80 MHz 85ns/66 MHz Max Min 11 20 Max ns 20 15 5 2 2 8 8 3 ns ns ns ns ns ns ns Units
Symbol tACLK tBOE tCLK tCSP tHD tKOH tOHZ tSP
Min 9
12.5 4 2 2
3
t CLK CLK V IH V IL t WC A[22:0] V IH V IL Valid Address t AVS t VPH ADV# V IH V IL t VP t CVS LB#/UB# V IH V IL t CW CE# V IH V IL (Note 2) OE# V IH V IL t WC t AS V IH V IL t CEW V OH V OL t WHZ DQ[15:0] V IH V IL High-Z DATA t DH DATA t DW V OH V OL High-Z t ACLK Valid Output t KOH Valid Output Valid Output Valid Output t BOE High-Z t WP t WPH t OHZ t CBPH t CSP t VS t BW t SP t HD t AVH t WC Valid Address t AW t WR t SP t HD t CKA t SP t HD
Valid Address
t SP
t HD
WE#
WAIT
Legend:
Don't Care
Undefined
Notes:
1. 1. Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay. When transitioning between asynchronous and variable-latency burst operations, CE# must go High. If CE# goes High, it must remain High for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See How Extended Timings Impact CellularRAMTM Operation for restrictions on the maximum CE# Low time (tCEM).
Figure 34.18
Asynchronous Write Followed by Burst Read
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Table 34.19
Write Timing Parameters--Asynchronous Write Followed by Burst Read
70ns/80 MHz 85ns/66 MHz Max Min 5 0 10 85 85 85 10 85 0 23 10 10 85 85 8 46 10 0 55 10 0 8 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Symbol tAVH tAS tAVS tAW tBW tCKA tCVS tCW tDH tDW tVP tVPH tVS tWC tWHZ tWP tWPH tWR
Min 5 0 10 70 70 70 10 70 0 20 10 10 70 70
Table 34.20
Read Timing Parameters--Asynchronous Write Followed by Burst Read
70ns/80 MHz 85ns/66 MHz Max 9 20 5 1 12.5 4 2 2 8 3 3 7.5 5 1 15 5 2 2 8 7.5 Min Max 11 20 Units ns ns ns ns ns ns ns ns ns ns
Symbol tACLK tBOE tCBPH tCEW tCLK tCSP tHD tKOH tOHZ tSP
Min
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t CLK CLK V IH V IL t WC A[22:0] V IH V IL Valid Address t WC Valid Address t AW t WR t SP ADV# V IH V IL t BW LB#/UB# V IH V IL t CW CE# V IH V IL (Note 2) OE# V IH V IL t WC t WP t WPH WE# V IH V IL t CEW WAIT V OH V OL t WHZ DQ[15:0] V IH V IL High-Z DATA DATA t DW V OH V OL High-Z t ACLK t KOH Valid Output Valid Output Valid Output Valid Output t BOE High-Z t SP t HD t OHZ t CSP t CSP t SP t HD t HD t CKA t SP t HD
Valid Address
t DH Legend:
Don't Care
Undefined
Notes:
1. 2. Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay. When transitioning between asynchronous and variable-latency burst operations, CE# must go High. If CE# goes High, it must remain High for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See How Extended Timings Impact CellularRAMTM Operation for restrictions on the maximum CE# Low time (tCEM).
Figure 34.19
Asynchronous Write (ADV# Low) Followed By Burst Read
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Table 34.21
Asynchronous Write Timing Parameters--ADV# Low
85ns/66 MHz Max Min 85 85 85 85 0 23 85 8 8 55 10 0 Max Units ns ns ns ns ns ns ns ns ns ns ns
70ns/80 MHz Symbol tAW tBW tCKA tCW tDH tDW tWC tWHZ tWP tWPH tWR 46 10 0 Min 70 70 70 70 0 23 70
Table 34.22
70ns/80 MHz Symbol tACLK tBOE tCBPH tCEW tCLK tCSP tHD tKOH tOHZ tSP 3 5 1 12.5 4 2 2 Min
Burst Read Timing Parameters
85ns/66 MHz Max 9 20 5 7.5 1 15 5 2 2 8 3 8 7.5 Min Max 11 20 Units ns ns ns ns ns ns ns ns ns ns
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t CLK CLK V IH V IL t SP t HD A[22:0] V IH V IL Valid Address t SP t HD ADV# V IH V IL t CBPH t HD t CSP CE# V IH V IL t BOE OE# V IH V IL t SP WE# V IH V IL t SP LB#/UB# V IH V IL t CEW V OH V OL t DW t ACLK DQ[15:0] V IH V IL High-Z t KOH Valid Output Valid Input t DH High-Z t KHTL t CEW High-Z t HZ t HD t BW t HD t OLZ t AS t WP t WPH t HZ (Note 2) t OHZ t CEM t CW t WC Valid Address t AW t WR
WAIT
Legend: READ Burst Identified (WE# = HIGH)
Don't Care
Undefined
Notes:
1. 2.
Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay. When transitioning between asynchronous and variable-latency burst operations, CE# must go High. If CE# goes High, it must remain High for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See How Extended Timings Impact CellularRAMTM Operation for restrictions on the maximum CE# Low time (tCEM).
Figure 34.23.
Burst Read Followed by Asynchronous Write (WE#-Controlled)
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Table 34.24
70ns/80 MHz Symbol tACLK tBOE tCBPH tCEW tCLK tCSP tHD tHZ tKHKL tKHTL tKOH tKP tOHZ 2 3 5 1 12.5 4 2 Min
Burst Read Timing Parameters
85ns/66 MHz Max 9 20 5 7.5 1 15 5 2 8 1.6 9 2 3 8 8 8 1.6 11 7.5 Min Max 11 20 Units ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 34.25
Asynchronous Write Timing Parameters--WE# Controlled
70ns/80 MHz 85ns/66 MHz Max Min Max 0 85 85 4 4 85 0 23 8 8 85 55 10 0 Units ns ns ns s ns ns ns ns ns ns ns ns
Symbol
tAS
Min 0 70 70
tAW tBW tCEM tCW tDH tDW tHZ tWC tWP tWPH tWR
70 0 23
70 46 10 0
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t CLK CLK V IH V IL t SP A[22:0] V IH V IL t HD Valid Address t AVS t SP t HD ADV# V IH V IL t AW t CBPH t HD t CSP CE# V IH V IL t BOE OE# V IH V IL t SP WE# V IH V IL t SP LB#/UB# V IH V IL t CEW V OH V OL t DW t ACLK DQ[15:0] V OH V OL High-Z t KOH Valid Output Valid Input t DH High-Z t KHTL t CEW High-Z t HZ t HD t BW t HD t OLZ t AS t WP t WPH t HZ (Note 2) t OHZ t AS t CEM t CW t VPH t VP t AVH t VS
Valid Address
WAIT
Legend: READ Burst Identified (WE# = HIGH)
Don't Care
Undefined
Notes:
1. 2.
Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay. When transitioning between asynchronous and variable-latency burst operations, CE# must go High. If CE# goes High, it must remain High for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See How Extended Timings Impact CellularRAMTM Operation for restrictions on the maximum CE# Low time (tCEM).
Figure 34.26.
Burst Read Followed by Asynchronous Write Using ADV#
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Table 34.27
70ns/80 MHz Symbol tACLK tBOE tCBPH tCEW tCLK tCSP tHD tHZ tKHKL tKHTL tKOH tKP tOHZ 2 3 5 1 12.5 4 2 Min
Burst Read Timing Parameters
85ns/66 MHz Max 9 20 5 7.5 1 15 5 2 8 1.6 9 2 3 8 8 8 1.6 11 7.5 Min Max 11 20 Units ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 34.28
Asynchronous Write Timing Parameters Using ADV#
85ns/66 MHz Max Min 0 5 10 85 85 4 4 1 85 0 23 8 8 10 10 85 55 10 0 7.5 Max Units ns ns ns ns ns s ns ns ns ns ns ns ns ns ns ns ns
70ns/80 MHz Symbol tAS tAVH tAVS tAW tBW tCEM tCEW tCW tDH tDW tHZ tVP tVPH tVS tWP tWPH tWR 10 10 70 46 10 0 1 70 0 23 Min 0 5 10 70 70
7.5
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A[22:0]
V IH V IL
Valid Address
Valid Address t AW t WR t AA
Valid Address
ADV#
V IH V IL t BW t BLZ t BHZ
LB#/UB#
V IH V IL t CW t CBPH t CEM t HZ
CE#
V IH V IL (Note) t LZ t OE t OHZ
OE#
V IH V IL t WC t AS V IH V IL t HZ V OH V OL t WHZ V IH V IL High-Z DATA t DH DATA t DW High-Z V OH V OL Legend: t OLZ t HZ t WP t WPH
WE#
WAIT
DQ[15:0]
Valid Output
Don't Care
Undefined
Note: CE# can stay Low when transitioning between asynchronous operations. If CE# goes High, it must remain High
for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See How Extended Timings Impact CellularRAMTM Operation for restrictions on the maximum CE# Low time (tCEM).
Figure 34.29.
Asynchronous Write Followed by Asynchronous Read--ADV# Low
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Table 34.30
Write Timing Parameters--ADV# Low
85ns/66 MHz Max Min 0 85 85 85 0 23 8 8 85 8 8 55 10 0 Max Units ns ns ns ns ns ns ns ns ns ns ns ns
70ns/80 MHz Symbol tAS tAW tBW tCW tDH tDW tHZ tWC tWHZ tWP tWPH tWR 46 10 0 70 Min 0 70 70 70 0 23
Table 34.31
70ns/80 MHz Symbol tAA tBHZ tBLZ tCBPH tCEM tHZ tLZ tOE tOHZ tOLZ 5 10 10 5 Min
Read Timing Parameters--ADV# Low
85ns/66 MHz Max 70 8 10 5 4 8 10 20 8 5 20 8 4 8 Min Max 85 8 Units ns ns ns ns s ns ns ns ns ns
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A[22:0]
V IH V IL
Valid Address t AVS t AVH
Valid Address t AW t WR
Valid Address t AA
t VPH t VP ADV# V IH V IL t CVS LB#/UB# V IH V IL t CW CE# V IH V IL
t VS
t BW
t BLZ
t BHZ
t CBPH
t CEM
t HZ
t AS V IH V IL t WC t AS V IH V IL V OH V OL t WHZ V IH V IL High-Z DATA t DH DATA t DW t WP t WPH
(Note)
t LZ
t OHZ
OE#
t OLZ
WE#
WAIT
t OE V OH V OL Legend: High-Z
DQ[15:0]
Valid Output
Don't Care
Undefined
Note: CE# can stay Low when transitioning between asynchronous operations. If CE# goes High, it must remain High
for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See How Extended Timings Impact CellularRAMTM Operation for restrictions on the maximum CE# Low time (tCEM).
Figure 34.32.
Asynchronous Write Followed by Asynchronous Read
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Table 34.33
Write Timing Parameters--Asynchronous Write Followed by Asynchronous Read
70ns/80 MHz 85ns/66 MHz Max Min 0 5 10 85 85 10 85 0 23 10 10 85 85 8 46 10 0 55 10 0 8 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Symbol tAS tAVH tAVS tAW tBW tCVS tCW tDH tDW tVP tVPH tVS tWC tWHZ tWP tWPH tWR
Min 0 5 10 70 70 10 70 0 23 10 10 70 70
Table 34.34
Read Timing Parameters--Asynchronous Write Followed by Asynchronous Read
70ns/80 MHz 85ns/66 MHz Max 70 8 10 5 4 8 10 20 8 5 5 10 20 8 10 5 4 8 Min Max 85 8 Units ns ns ns ns s ns ns ns ns ns
Symbol tAA tBHZ tBLZ tCBPH tCEM tHZ tLZ tOE tOHZ tOLZ
Min
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35 How Extended Timings Impact CellularRAMTM Operation
35.1 Introduction
This section describes CellularRAMTM timing requirements in systems that perform extended operations. CellularRAM products use a DRAM technology that periodically requires refresh to ensure against data corruption. CellularRAM devices include on-chip circuitry that performs the required refresh in a manner that is completely transparent in systems with normal bus timings. The refresh circuitry imposes constraints on timings in systems that take longer than 4s to complete an operation. Write operations are affected if the device is configured for asynchronous operation. Both Read and Write operations are affected if the device is configured for page or burst-mode operation.
35.2
Asynchronous Write Operation
The timing parameters provided in Figure 34.4 require that all Write operations must be completed within 4s. After completing a Write operation, the device must either enter standby (by transitioning CE# High), or else perform a second operation (Read or Write) using a new address. Figure 35.1 and Figure 35.2 demonstrate these constraints as they apply during an asynchronous (page-mode-disabled) operation. Either the CE# active period (tCEM in Figure 35.1) or the address valid period (tTM in Figure 35.2) must be less than 4s during any Write operation, otherwise, the extended Write timings must be used.
tCEM < 4 s CE# ADDRESS
Figure 35.1
Extended Timing for tCEM
CE# tTM < 4s ADDRESS
Figure 35.2 Table 35.1
Page Mode Asynchronous Page Mode Disabled Asynchronous Page Mode Enabled Burst
Extended Timing for tTM
Extended Cycle Impact on Read and Write Cycles
Read Cycle No impact. Write Cycle Must use extended Write timing. (See Figure 35.2) Must use extended Write timing. (See Figure 35.3)
Timing Constraint tCEM and tTM > 4s (See Figure 35.1 and Figure 35.2.) tCEM > 4s (See Figure 35.1.) tCEM > 4s (See Figure 35.1.)
All following intrapage Read access times are tAA (not tAPA).
Burst must cross a row boundary within 4s.
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35.2.1
Extended Write Timing-- Asynchronous Write Operation
Modified timings are required during extended Write operations (see Figure 35.3). An extended Write operation requires that both the Write pulse width (tWP) and the data valid period (tDW) be lengthened to at least the minimum Write cycle time (tWC [MIN]). These increased timings ensure that time is available for both a refresh operation and a successful completion of the Write operation.
t CEM or t TM > 4s ADDRESS
CE#
LB#/UB# t WP > t WC (MIN) WE#
t DW > t WC (MIN) DATA-IN
Figure 35.3
Extended Write Operation
35.3
Page Mode Read Operation
When a CellularRAM device is configured for page mode operation, the address inputs are used to accelerate Read accesses and cannot be used by the on-chip circuitry to schedule refresh. If CE# is Low longer than the tCEM maximum time of 4s during a Read operation, the system must allow tAA (not tAPA, as would otherwise be expected) for all subsequent intrapage accesses until CE# goes High.
35.4 Burst-Mode Operation
When configured for burst-mode operation, it is necessary to allow the device to perform a refresh within any 4s window. One of two conditions will enable the device to schedule a refresh within 4s. The first condition is when all burst operations complete within 4s. A burst completes when the CE# signal is registered High on a rising clock edge. The second condition that allows a refresh is when a burst access crosses a row boundary. The row-boundary crossing causes Wait to be asserted while the next row is accessed and enables the scheduling of refresh.
35.5
Summary
CellularRAM products are designed to ensure that any possible asynchronous timings do not cause data corruption due to lack of refresh. Slow bus timings on asynchronous Write operations require that tWP and tDW be lengthened. Slow bus timings during asynchronous page Read operations cause the next intrapage Read data to be delayed to tAA. Burst mode timings must allow the device to perform a refresh within any 4s period. A burst operation must either complete (CE# registered High) or cross a row boundary within 4s to ensure successful refresh scheduling. These timing requirements are likely to have little or no impact when interfacing a CellularRAM device with a low-speed memory bus.
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36 Revisions
Revision A0 (February 17, 2005)
Initial Release
Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion LLC will not be liable to you and/or any third party for any claims or damages arising in connection with abovementioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion LLC product under development by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright (c)2004-2005 Spansion LLC. All rights reserved. Spansion, the Spansion logo, and MirrorBit are trademarks of Spansion LLC. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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